In this role I act as a runtime system software architect as part of the product planning team. I am responsible specifically for the automotive market segment. In addition, I collaborate with my peers to ensure that the runtime software needs of all market segments are represented in the greater Xilinx runtime software architecture.

In this role I act as a runtime system software architect as part of the product planning team. I am responsible specifically for the automotive market segment. In addition, I collaborate with my peers to ensure that the runtime software needs of all market segments are represented in the greater Xilinx runtime software architecture.

In this role I was responsible for developing and delivering technical training content for the Xilinx internal stakeholders company-wide as well as for our worldwide customer base. Examples of this content includes white papers, lectures and labs for our annual technical sales conference, and on-demand collateral to meet the needs of our key customers.

In this role I was a key stakeholder within the Xilinx embedded Linux community. I worked directly with customers, engineering stakeholders, and marketing to craft Xilinx's embedded operating system products and their support model. In addition, I consulted directly with our customers to provide solutions for their most demanding applications of our technology.I was directly responsible for the Xilinx support model of embedded Linux (including U-Boot, the Linux kernel, and Linux userspace) as well as the PetaLinux toolchain. I coordinated the efforts of a team of engineers at Xilinx support sites worldwide to ensure that the customer experience is consistent and effective.As a hands-on advocate for the needs of our users, I routinely engaged in one-on-one training with our customers and field support engineers to ensure that their experience with Xilinx products is world class.

As a member of the hardware skillset Product Applications team, I directly worked with customer to triage and debug question related to the Xilinx FPGA families. Common inquiries included everything from debugging JTAG and boundary scan interfaces to pinout and floorplanning recommendations. My expertise in this domain was the Xilinx high-speed Multi-Gigabit Transceivers (MGTs) for Xilinx 4-, 5- and 6-series families.

In this role, I worked directly with Xilinx customers through all phases of their design entry and implementation. As such, I was equally conversant discussing GUI usage and HDL coding best practices with customers as I was in drilling down to the silicon-level implementation of their design to ensure that they were able to make the most effective use of our devices.In addition, I had to be familiar with all phases of FPGA design flow – tool licensing, design entry, design constraining, design simulation, synthesis and implementation, and timing closure. To be effective I was familiar with the full spectrum of Xilinx design tools – Project Navigator, PlanAhead, XST synthesis, place and route (MAP/PAR), ChipScope, and most recently Vivado (including IPI).I specialized in design entry (Project Navigator, PlanAhead, and Vivado) and implementation (netlist translate, mapping, place & route).

•Converted PCI form factor video capture devices to CardBus form factor•Design management -- including schematic entry, mixed SMT and thru-hole PCB layout, BoM management.•Authored internal development plan for migration to Texas Instruments xDAIS / xDAIS-DM API.•Authored system requirements for a low-power system based around the Freescale MPC5200B microprocessor.