Tri Phan Email & Phone Number

Melbourne, VIC, AU

Saitama, Japan

More than 2 years experienced as DFT engineers, such as scan chain insertion, MBIST insertion and MBIST verification, ATPG pattern generation and verification. Support other task as customer requests (design, verify, synthesis, timing check)

Ho Chi Minh City, Vietnam

4+ years experience in Circuit design, perform characterize/racing/margin check for TCAM IP, Dualport Sram IP, optimize memory performance. Perform function check for memory IP (both GLN & SPICE netlist), equivalent check between Spice & Verilog, Spice & GLN netlist. Building CCSN & ECSM libraries for memory. Ensure the quality of result before delivery.

Ho Chi Minh City, Vietnam

• 4+ years experience in Middle-end field for ASIC designs, perform timing check by trial synthesis to ensure design quality and perform Middle-End task (such as: synthesis, SDC management, analyze reports, check and fix.
• Experienced in build environment & perform synthesis by Design Compiler, equivalent check (netlist vs netlist, netlist vs RTL, RTL vs RTL) by… Show more
• Experienced in build environment & perform synthesis by Design Compiler, equivalent check (netlist vs netlist, netlist vs RTL, RTL vs RTL) by Formality & Conformal, timing check by using PrimeTime. Confirm & manage.
• 3+ years experience in MCU verification, IP specification definition, develop peripheral module specification as customer's requirement. RTL (Verilog) design know-hows.
• Experienced in data transfer among different clock domain handling (both synchronous and asynchronous), SoC bus system including high speed bus (AXI, SHwy), and peripheral bus (APB, HPB).
• Experience in RTL coding & verification to check coding rule, build environment to verify RTL function at Unit-Test level & Compile-Test level (model, test bench, code coverage, assertion-based verification), perform.