• Design of high-speed 256:64 CMOS Serializer (schematic, layout, PLS): - 16:4 core serializer units - High-speed, zero-skew clock tree - Clock dividers and reset circuitry - CML to CMOS and CMOS to CML converters• Design of OTAs and voltage references in various CMOS technology nodes including 22 nm FDSOI and 65 nm (schematic, layout, PLS)• Top level schematic, layout and simulation: - Floorplan - DRC, LVS, PEX - Dummy filling and density checks• I/O ring design• Behavioral modeling using Verilog-A• Custom digital design using: - Standard cells - Self-designed register and gates• Design of high speed frequency divider (schematic, layout, PLS)• Design of high speed clock receiver (schematic, layout, PLS)• Design of CML driver (schematic, layout, PLS)• Design and optimization of CML units operating at different frequencies including: - CML Buffer - CML MUX - CML Latch• Documentation for various designs