Tu Rivera, Pmp work email
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Tu Rivera, Pmp personal email
Program Manager || Project ManagerDesign and deliver quality products while meeting project deadline and costs. Confer with engineering staff from project inception to delivery through the manufacturing process to meet go to market plans. Expertise in lean operations, hands-on system development from cradle to mass production, and coordinate across multi-functional task force teams to expedite to solutions. Enjoys in being in critical path to be the driving role in launching products.Over fifteen years experience in the digital data storage for a Fortune 500 organizations.
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Technical Program ManagerGoogle Aug 2019 - Nov 2023Sunnyvale
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Program Manager - Installed SystemsQsc Sep 2016 - Aug 2019Costa Mesa, CaliforniaWorking on strategic and tactical projects to bring Audio, Visual, and Control system-level solutions into boardrooms, theme parks, transportation (airports, cruise ships, rail) and small-to-large entertainment venues. -
Engineering Program Manager | Program ManagerWestern Digital Jul 2012 - Oct 2015Irvine, California• Led and launched products on WD My Passport and My Book product lines; including the first launch of Thunderbolt2 on WD’s My Book Pro• Collaborated with multiple inter-departmental teams to meet product goals• Presented program status via video and in-person conferencing to stakeholders weekly• Created project schedule, labor resource plans, project build plans, and development budget plans ensuring product’s milestones are met• Collaborated with HDD teams to define and develop features to meet NAS and SMB use cases:o Servo power requirements under WiFi, Networking, TBT, and USB environmentso PCBA designs for each targeted countries’ ESD and Environment requirementso Channel signal analysis on ASICs to modulate EMI and RF discrepancies• Identified new methodologies to increase performance by 7% on top selling SKUs to grow products’ marketability• Derived assembly methodologies with ME and NPI to prevent VMI issues on manufacturing lines• Selected hardware to ship to Intel, Apple, ASMedia, JMicro, and GRL for joint Thunderblot 2 compliance qualification• Managed the qualification of USB Bridge ASICs through initial designs and authored flowcharts for full qualification before admitting part on to product’s BOMsSome of the links below are a few of the products I've managed and launched in my role as a PM/EPM. -
Senior Principal System Design EngineerWestern Digital Jan 2009 - Jul 2012Irvine, Ca• Launched largest capacity points with new Marvell SOC on both 2.5” and 3.5” Client programs as lead systems engineer• Delivered daily status to local functional and Asia teams during development and low volume manufacturing• Facilitated brainstorming sessions to create short and long tasks for product delivery, which improved development times• Collaborated with NPI to transfer programs from onsite development to HVM in overseas factories• Staged and developed the Psuedo-Shingle technology for a 20% increase in aerial density• Assisted with op-vibe/shock data collection and analysis on Amazon, Google, and Facebook data server systems to design a better Servo PWUS/WUS data prediction algorithms• Build, test, and modified reliability fixtures to accommodate for various USB ASIC vendors at a manufacturing scale• Was acting NPI and EPM on Helium-filled experiment on a 4-platter HDD
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Senior Firmware Engineer | Embedded Fw Designer | Plsi ValidationWestern Digital Aug 2007 - Dec 2008Lake Forest, Ca• Support servo engineer for Spindle tuning and resolving fatal issues discovered during ASIC bring-up• Completed spin-up and spindle tuning within 1-month of ASIC reception as lead engineer• Tested and verified new PLSI ASICs and motors for functionality and to minimize mechanical audible output• Promoted to System Engineer after 1 year as PLSI Firmware
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Quality Test Engineer | Firmware Test EngineerWestern Digital Jun 2005 - Aug 2007Lake Forest, Ca• Challenged and developed failure analysis capabilities by demanding to lead latest product• Discovered HOM timing issues due to PATA to SATA commands translation and prevented quality excursion at major OEMs• Requested to lead highest capacity point aerial density program to challenge and build FA capabilities on ATA7 Streaming feature set to set-top box customers• Designed and build test plans to qualify multiple OEM customers for initial and maintenance firmware releases• Provided technical support with Asia counterparts to reproduce test issues to streamline failure analysis to root cause• Lead daily test summary meetings with Program and functional stakeholders and teams to report and resolve any quality issues• Collaborated with colleagues to determine firmware systematic issues across projects to expedite products release to production
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Quality Test Engineer | Firmware Test EngineerQuantum Corporations Dec 2004 - Jun 2005Irvine, Ca• Tested tape libraries and 6x16-HDD arrays to complete quality testing before releasing to manufacturing and/or new FW to customers• Wrote detailed test plans and completed tests on tape libraries and HDD arrays per customers’ application specifications -
InternLinksys - Cisco Company Jun 2004 - Aug 2004Irvine, Ca
Tu Rivera, Pmp Skills
Frequently Asked Questions about Tu Rivera, Pmp
What is Tu Rivera, Pmp's role at the current company?
Tu Rivera, Pmp's current role is Technical Program Manager | Program Manager | System Design and Integration | NPI Operations | Mass Production.
What is Tu Rivera, Pmp's email address?
Tu Rivera, Pmp's email address is tu****@****gle.com
What schools did Tu Rivera, Pmp attend?
Tu Rivera, Pmp attended Uc Irvine, Uc Irvine.
What skills is Tu Rivera, Pmp known for?
Tu Rivera, Pmp has skills like Asic, Soc, Sata, Testing, Program Management, Engineering, Usb, Firmware, Debugging, Embedded Systems, Storage, Arm.
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