Taylor Womack Email & Phone Number

Portland, OR, US

Santa Clara, California, US

• Frontend design engineer working on IP RTL design/integration with substantial experience in post-silicon debug. My work requires strong teamwork/collaboration skills as well as intimate knowledge of frontend tools.
• 7+ years in power management IP RTL design. Implemented features requiring close coordination with verification, architecture, and firmware teams for scope/complexity analysis and schedule alignment. Wrote unit- and.
• 2.5+ years full-time in post-Si debug with high-impact contributions across multiple projects. Ran several task forces debugging critical issues, facilitating collaboration between post-Si validation, pre-Si.
• Successfully organized GPIO RTL integration, which had global die impact and complex topological changes. Led GPIO design paranoia effort to debug integration/architectural problems. Provided support to backend.
• Strong scripting accomplishments, including automatic version control status updates, model performance data analysis, static checker for IP topology changes, and tracker for IP content syncs
• Various professional activities, including administering technical interviews, technical/professional mentoring, and writing for internal technical journal

Pittsburgh, PA, US

TA'd for 4 semesters during undergrad and grad school in the Dept. of ECE (logic design/verification) and School of CS (introductory programming).

Pittsburgh, PA, US

Provided individual and group tutoring sessions for fellow Carnegie Mellon students in various freshman and sophomore-level engineering/computer science courses.

Pittsburgh, PA, US

• Assisted graduate student in Computer Architecture Lab at Carnegie Mellon (CALCM) with thesis research work by developing a benchmarking tool:
• Developed a microbenchmark generation tool in Perl for an experimental FPGA memory architecture
• Automatically generated and compiled C control threads and Verilog designs to fit user-inputted testing parameters
• Measured throughput and bandwidth between memory and BRAM blocks with varying levels of parallelism

Santa Clara, California, US

• Spent the summer at Intel working on validation tool integration for SoCs:
• Brought up and debugged fabric traffic test generator tool for Intel SoC product
• In charge of tool set up, methodology, environment, teaching colleagues about tool, and debugging

San Diego, CA, US

• Engaging summer internship with Qualcomm's Snapdragon SoC hardware verification team:
• Updated legacy SoC test environment, requiring knowledge of standard OVM methodologies
• Translated legacy Vera/VHDL/Verilog tests into SystemVerilog/UVM with Perl scripts
• Ran regressions to ensure correct translation of test content

Master Of Science (M.S.), Electrical And Computer Engineering

Bachelor Of Science (B.S.) With University Honors, Electrical And Computer Engineering