Taylor Womack Email & Phone Number

Portland, Or, Us

Santa Clara, California, Us

Frontend design engineer working on IP RTL design/integration with substantial experience in post-silicon debug. My work requires strong teamwork/collaboration skills as well as intimate knowledge of frontend tools (Lint, UPF, CDC, RDC, FEV, VCS, Verdi, etc.), deep understanding of IP/SoC architectures, and strong scripting/programming skills. Some highlights below:• 7+ years in power management IP RTL design. Implemented features requiring close coordination with verification, architecture, and firmware teams for scope/complexity analysis and schedule alignment. Wrote unit- and IP-level tests. Defined and implemented various DFX features. Supported SoC integration and IP/SoC-level verification teams• 2.5+ years full-time in post-Si debug with high-impact contributions across multiple projects. Ran several task forces debugging critical issues, facilitating collaboration between post-Si validation, pre-Si verification, architecture, firmware, and design teams. Brought design learnings from post-Si debug into design for future products. Experienced with architecting solutions (HW and SW) under time-critical pressure. Experienced with scan capture/analysis, trace capture/analysis, FIB circuit edits, debug scripting, and lab equipment (e.g., logic analyzers, chillers, platform tools, BIOS/FW stitching, platform setup for issue reproduction, etc.)• Successfully organized GPIO RTL integration, which had global die impact and complex topological changes. Led GPIO design paranoia effort to debug integration/architectural problems. Provided support to backend designers and verification teams on design changes/impact• Strong scripting accomplishments, including automatic version control status updates, model performance data analysis, static checker for IP topology changes, and tracker for IP content syncs• Various professional activities, including administering technical interviews, technical/professional mentoring, and writing for internal technical journal

Pittsburgh, Pa, Us

TA'd for 4 semesters during undergrad and grad school in the Dept. of ECE (logic design/verification) and School of CS (introductory programming).

Pittsburgh, Pa, Us

Provided individual and group tutoring sessions for fellow Carnegie Mellon students in various freshman and sophomore-level engineering/computer science courses.

Pittsburgh, Pa, Us

Assisted graduate student in Computer Architecture Lab at Carnegie Mellon (CALCM) with thesis research work by developing a benchmarking tool:• Developed a microbenchmark generation tool in Perl for an experimental FPGA memory architecture• Automatically generated and compiled C control threads and Verilog designs to fit user-inputted testing parameters• Measured throughput and bandwidth between memory and BRAM blocks with varying levels of parallelism

Santa Clara, California, Us

Spent the summer at Intel working on validation tool integration for SoCs:• Brought up and debugged fabric traffic test generator tool for Intel SoC product• In charge of tool set up, methodology, environment, teaching colleagues about tool, and debugging

San Diego, Ca, Us

Engaging summer internship with Qualcomm's Snapdragon SoC hardware verification team:• Updated legacy SoC test environment, requiring knowledge of standard OVM methodologies• Translated legacy Vera/VHDL/Verilog tests into SystemVerilog/UVM with Perl scripts• Ran regressions to ensure correct translation of test content

Master Of Science (M.S.), Electrical And Computer Engineering

Bachelor Of Science (B.S.) With University Honors, Electrical And Computer Engineering