Uday Devanagundy

Uday Devanagundy Email and Phone Number

Associate Director for Software development, QA, DevOps, and Tech Pubs. @ Microchip Technology Inc.
Corporate Headquarters Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, Arizona, USA 85224-6199
Uday Devanagundy's Location
Austin, Texas, United States, United States
Uday Devanagundy's Contact Details

Uday Devanagundy work email

Uday Devanagundy personal email

About Uday Devanagundy

Seasoned professional with more than 25 years experience in VLSI/ASIC/FPGA design and verification, project and people management.Areas of Technical Expertise: - ASIC/SoC flow: Design, verification, timing closure, tape-out and post-silicon validation. - FPGA flow: Architecture, design, advanced debug, programming. - Domains: Storage area (SCSI, Fibre Channel, SATA), PCI series, intra-chip (AHB etc.)Product development/Project execution expertise: - Deep focus on Reuse methodology - Improve efficiency through automation - Ensure quality is top priorityMy Specialties: - Managing and sustaining high performance teams - Innovation - Mentoring

Uday Devanagundy's Current Company Details
Microchip Technology Inc.

Microchip Technology Inc.

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Associate Director for Software development, QA, DevOps, and Tech Pubs.
Corporate Headquarters Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, Arizona, USA 85224-6199
Website:
microchip.com
Employees:
10
Company phone:
(480) 792-7200
Uday Devanagundy Work Experience Details
  • Microchip Technology Inc.
    Senior Engineering Manager
    Microchip Technology Inc. May 2018 - Present
    Chandler, Az, Us
  • Microsemi Corporation
    Engineering Manager
    Microsemi Corporation Aug 2016 - May 2018
    Aliso Viejo, Ca, Us
  • Teq.E.I.S. Smart Solutions
    Founder
    Teq.E.I.S. Smart Solutions Jul 2015 - Jul 2016
    Stealth mode product development for Smart City Transport and Education.Freelance instructor specializing in: - ASIC chip design and verification: methodology, and practical implementation - FPGA: Architecture, design, programming and debug - Protocols: Application and implementation
  • Xilinx
    Sr. Engineering Manager - Validation And Sign-Off Major Vivado And Ise Features
    Xilinx Feb 2010 - Jul 2015
    San Jose, Ca, Us
    Validation and sign-off for ISE and Vivado software components such as Synthesis, Simulator, Power tools (XPE and Report Power), Chipscope, iMPACT, Labtools, Encryption.Championed Vivado software component validation on hardware.- Review release features and develop validation strategy- Resource planning and contingency- Review and report to management- Feature sign-off
  • Pw Systems/Elloka Techsolutions
    Vp Of Engineering: Soc Architecture, Design, And Verification.
    Pw Systems/Elloka Techsolutions Nov 2008 - Nov 2009
    I headed a team that was designing a low cost computer targeted to rural areas.- Involved in SoC and product planning- Prepared product Proof-Of-Concept on FPGA which was demo-ed at Comdex.- Worked with 3rd party vendors for design and verification IPs.- Guided team of ASIC design and verification engineers
  • Synopsys
    Vg Cae Manager (Vcs, Dve, Ucli, Leda)
    Synopsys Aug 2005 - Oct 2008
    Sunnyvale, California, Us
    Managed a team of engineers responsible for customer support for DVE and UCLI, Leda, and VCS (core VCS, Verilog, and SystemVerilog).Managed key customer accounts across different geographies.Strategic analysis of competitive landscape, drive tool enhancements, and coordinate validation activities.
  • Sun Microsystems
    Staff Engineer - Verification
    Sun Microsystems Aug 2004 - Aug 2005
    Palo Alto, Ca, Us
    Responsible for verification of Data and Memory management sub-blocks in the 8-core, 64-thread Sparc T2 processor.The design was created with Verilog and the verification environment was built using SystemVerilog.
  • Ario Data Networks
    Verification Manager: Fc, Sata, And Arm Soc
    Ario Data Networks Jul 2001 - Aug 2004
    Us
    Designed Fibre Channel Arbitrated Loop master and prototyped on FPGA with FC hard drives.Verification manager for FC to SATA RAID controller. - SATA and Fibre Channel verification models in SystemVerilog - SystemVerilog Full chip verification platform based with ARM, FC, SATA, and DDR. - Validated on FPGAOther responsibilities:- Coordinate verification and board validation effort- Work with vendors for 3rd party tools and evaluation and resources- Focal point for verification code review and automation
  • Adaptec
    Asic Design Engineer: Fc And Scsi Products
    Adaptec 1994 - 2000
    Us
    Designed Memory interface for Fibre channel host adapter, AIC-1160, Command channel module for SCSI solutions, and full chip integration.Worked on design, RTL and firmware verification, full chip timing closure and pinout.

Uday Devanagundy Skills

Asic Verilog Soc Fpga Functional Verification Systemverilog Debugging Rtl Design Embedded Systems Perl Vlsi Eda Tcl Xilinx Semiconductors Field Programmable Gate Arrays System On A Chip Application Specific Integrated Circuits Automation Validation Very Large Scale Integration Asic And Fpga Development

Uday Devanagundy Education Details

  • Louisiana State University
    Louisiana State University
    E.E.
  • Sri Jayachamarajendra College Of Engineering
    Sri Jayachamarajendra College Of Engineering
    It

Frequently Asked Questions about Uday Devanagundy

What company does Uday Devanagundy work for?

Uday Devanagundy works for Microchip Technology Inc.

What is Uday Devanagundy's role at the current company?

Uday Devanagundy's current role is Associate Director for Software development, QA, DevOps, and Tech Pubs..

What is Uday Devanagundy's email address?

Uday Devanagundy's email address is ud****@****hoo.com

What schools did Uday Devanagundy attend?

Uday Devanagundy attended Louisiana State University, Sri Jayachamarajendra College Of Engineering.

What are some of Uday Devanagundy's interests?

Uday Devanagundy has interest in Science And Technology, Children, Education.

What skills is Uday Devanagundy known for?

Uday Devanagundy has skills like Asic, Verilog, Soc, Fpga, Functional Verification, Systemverilog, Debugging, Rtl Design, Embedded Systems, Perl, Vlsi, Eda.

Who are Uday Devanagundy's colleagues?

Uday Devanagundy's colleagues are Gilbert Laurel, Ivan Art Caberte, Arun Kumar J, Mohd Anas Siddiqui, Trilok Varma, Anand Paul, Pamidi Akanksha.

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