Experienced Design Verification Engineer with expertise in developing RTL models, test benches, and test cases using Verilog, SystemVerilog, and UVM. Demonstrated expertise in enhancing functional coverage, debugging, and delivering substantial Business Value Additions through automation.Seeking to leverage my skills and experience in a role as an ASIC/IP Design Verification Engineer.• Working on Intel RDMA( Remote Direct Memory Access) Protocol Engine design for versatile SOC integration in TSMC 5nm.• Worked on SPEC2JEM Tracker Integration enhancements .• Worked on Execution of Gate Level Simulation (GLS) Validation for Intel's cutting-edge Graphics IPs, including XE2. • Contributed 6 Python automation scripts, with 2 recognized as Business Value Additions for Intel.HDL : VerilogHVL : System Verilog, System Verilog AssertionsMethodology : Universal Verification Methodology(UVM)Knowledge : Digital design, RTL coding, FSM based Design, Remote Direct Memory Access (RDMA), RoCE protocol ,Digital Electronics, Python Scripting, C language ,Commands( linux, unix, git , vim editor), Hands on Debug Experience in Gate Level Simulation using VERDI.Automations using Python script:-1. Automating file comparison and conversion between Git repositories: $4,423.2 Saved Per Year.2. Automated the merging and pulling of repository changes, preventing conflicts: $4,783.44 Saved Per Year.3. Automation script for monitoring Scheduled packet arbitration (QSET based): $14,573.76 Saved Per Year.4. Automation for enabling tests in different configuration modes: $950 Saved Per Year.5. Automated Regression Report Generator and Failure Categorization: $36,000 Saved Per Year.6. Automation for TI , Only on Clean Regression