Physical Design Engineer
CurrentKey Responsibilities.• Block level PnR (Synthesis, Floorplan, placement, CTS, Routing) with clean signoff checks.• FPGA SoC Full chip Integration (Bump planning, Robust RDL Routing with Bumps, Pin assignment for blocks / Floorplan)• Physical verification (DRC, LVS, ANT) , LEC at block level / Chip levelHands on experience on Commercial and Open source tools.Tools Used:Synopsys Fusion Compiler, IC Validator, PrimeTime, Formality, StarRC, VCS, Verdi, Yosys, OpenFPGA.