1.Hands on experience in FPGAs development, algorithm implementation, and system-level design2. Hands-on experience in writing RTL level code(verilog and VHDL) 3. Designed and implemented system-level models using Simulink, and convert them into HDL utilizing Simulink HDL Coder4. Developed Communication protocols in Verilog including UART, SPI and TCP5. Utilized Vivado IPs for design purposes wherever required including FIFOs, BRAMS, DDS, FFT, FIR filters, and Channelizer etc.

Developed code-level energy estimation framework for embedded soft-core processors. The framework is useful for algorithm developers to aware them regarding power consumption on the target processor before running that algorithm.