Sumit Kumar Email & Phone Number

Seattle, WA, US

Philadelphia, PA, US

• Led a team of five individuals to evaluate idea innovation pipeline and transformed existing innovation management systems & practices for a fast-growing semiconductor equipment firm with market cap of $2.2B.
• Redefined purpose statement, initiated cultural movement, installed innovation collaboration hub with budget reallocation for transformative tech and identified measurable innovation metrics to monitor P&L.

San Jose, CA, US

• Developed innovative business models to manage product cost vs. feature trade-off resulting in $65M+ saving, enabled competitive positioning with state-of-the-art IP sourcing to improve client SSD storage products.
• Partnered with finance, engineering and quality teams to define product cost roadmap, aligned executive audience with silicon sourcing strategies, spearheaded 20+ contract negotiations for HDD/flash storage products to.
• Drove organizational transformation with source to pay strategic initiative, improved should cost adherence from 28% to 60%, established executive, strategic and functional KPIs to benchmark against best industry.

Santa Clara, California, US

• Defined substrate technology strategy, design architecture, specs and critical metrics, managed program roadmaps through development, qualification and ramp while leading a team of 15+ module engineers to develop.
• Achieved product cost savings of ~$400M through substrate supplier capex cost-avoidance, substrate material and process improvements, and product design enhancements. These savings equated to ~20% of overall substrate.
• Drove executive decision and strategic initiative while managing ambiguity and risks to enable Intel’s first novel in-house stiffener process to overcome generational chip attach yield challenges.

Santa Clara, California, US

• Led modules, design, substrate, reliability and factory teams to develop assembly and test technology for Intel’s first many-integrated-core supercomputer product and certified for ramp within one year, prevented.
• Defined Intel’s Xeon family server CPU package architecture, optimized test vehicle design coverage to save $10M in tooling costs, developed award winning lean factory transfer methodology to enable faster.
• Improved assembly modules data integrity indicators from 50% to >99.75% within 6 months to meet assembly target yields and manage defect escapee risks to customers.

Santa Clara, California, US

• Led projects to develop, ramp and sustain new process technologies for CPU and chipsets manufacturing, reduce BOM costs, improve equipment utilization and ensure “copy exact” process transfers to other high-volume.
• Led effective process control and monitoring with equipment maintenance during various technology cycles while balancing the demands of cost, quality and output to achieve best product while ensuring profitability.
• Managed a group of technicians to enable operational improvements to maximize factory output, efficiency and productivity by 30% over the life of product life cycle.

Santa Clara, California, US

o Developed advanced metallographic methods to analyze crack propagation and failure characteristics of package and motherboard level solder jointso Established microstructure enhancement BKMs for optimal imaging using EBSD and cross-polarizing microscope.

New Delhi, Delhi, IN

Development of blackening process in shadow mask processing and manufacturing (TV cathode ray tubes)

Master Of Business Administration - Mba, Finance, Entrepreneurial Management And Innovation

Ms And Phd, Nanoscale Science And Engineering

B.Tech, Materials And Metallurgical Engineering