Daniel Kho, Smieee Email & Phone Number

Singapore

Mukim 18 Tanjung Tokong, Penang, My

- Chief Architect, Digital and AMS Full Chip Design- Architect, Video and Digital Signal Processing- Architect, Serial and Wireless CommunicationsProduct Development------------------------- Led the development of a video processor IP core.- Led the integration of AI core.- Led the development of communications IP cores: FFT, QPSK/QAM, MIPI C-PHY.- Designed and verified SPI interface IP.- Led the development of QSPI interface IP core.- Developed closed-loop servo control system and gyroscope sensor acquisition for marine control surfaces.- Designed and verified pseudorandom number generators, including LFSRs based on Galois field, and Mersenne twister.- Designed and verified a Blowfish cryptographic core.- Developed generic standard cell library for easy porting between FPGA and ASIC.- Modelled, designed, and verified an area-optimised, parameterisable n-order digital FIR filter.- Designed and verified an AXI4-Stream interface IP.- Led the development of AXI4-Lite interface IPs.Design Services------------------------- VHDL RTL design, bus interfaces, RISC processors, custom logic- VHDL scoreboards, interfaces (record ports)- OSVVM constrained random verification (CRV) and functional coverage (FC)- VHDL TLM and BFM, stimuli generators, transaction monitorsClassroom Training----------------------------- Provide dedicated or classroom training for digital design, digital signal processing, digital communications, and digital control.- Participants learn industry-standard languages and methodologies such as VHDL, PSL, OSVVM, SystemVerilog, UVM, bash, csh, Perl, Python, and Tcl. Emphasis on hands-on learning using practical tools such as VCS-MX, Design Compiler, Questa/ModelSim, Vivado, Quartus, Matlab, and Sage.Visit www.logik.haus to find out more, or email me (daniel [dot> kho <​at] logik.haus) for a more personal touch.--Daniel Kho @ LogikHausdaniel.kho <​at] logik.haus | www.logik.haus | Phone: +65-8832-4546 / +65-8874-0726

Singapore, Singapore, Sg

- Involved in ASIC-FPGA co-design and co-simulation flows.- First to enhance existing ASIC functional simulation flow to support FPGA functional simulations.

- Responsible as company-wide Lead Engineer for several design service projects.- Responsible as Principal Trainer for technical training programmes.- Provided consulting, training, and design services to customers in areas of FPGA, IC Design, and DSP. Trained digital engineers in VHDL, Verilog, SystemVerilog, and UVM.- Appointed Consultant Trainer to Integrated Circuit Engineering (ICE). Given trainings in SystemVerilog and UVM using Synopsys design and verification tools.- Appointed Consultant engineer to Usains Infotech Sdn. Bhd. Provided training services in VHDL and SystemVerilog using Synopsys tools.- Appointed FPGA design architect for Sophic Automation.

- Founder of a small sole-proprietorship, Tauhop Solutions.- Responsible as consulting engineer for technical training programmes.- Provided consulting, training, and design services to customers in areas of FPGA, IC Design, and DSP. Trained digital engineers in VHDL, Verilog, SystemVerilog, and UVM.- Appointed FPGA architect for a marine electronics control system project. System-level architecture and microarchitecture planning, definition, design, and verification of industrial marine electronics targeting FPGAs and ASICs. A patent incorporating some of my basic ideas have been filed.- Collaborated with Collaborative Microelectronics Design Excellence Centre (CEDEC), Universiti Sains Malaysia, in developing a hardware-based Blowfish cryptographic system. Several papers have been published.- Certified Train-the-Trainer (HRDF Malaysia) and Certified Professional Trainer (IPMA, UK).

Chicago, Il, Us

Notable accomplishments:- Involved in a mission-critical and safety-critical telecommunications basestation design project.- Bus protocol design: First to introduce synthesisable BFM technique, and VHDL Interfaces (record ports) technique for bus protocol design. Designed bus protocols for AXI, Avalon, and SPI using these VHDL techniques.- DSP: temperature conversion.- Hardware BiST/DFT design. Uses synthesisable BFM technique.- Simulation testbench design: Constrained random verification (CRV) testbench, hierarchical / external names, and assertions-based verification (ABV) using embedded PSL.- SoC design: system-level integration of subsystems interconnected with Avalon, AXI busses. Subsystem IP design with Avalon-compliant interface (designed with synthesisable BFM technique and VHDL Interfaces).- Physical / layout / structural design: First to introduce floorplanning, design partitioning, and design preservation concepts to the FPGA team.

Tempe, Arizona, Us

Notable accomplishments:- Involved in FPGA chip microarchitecture definition for a safety-critical precision motion control system. Written a block-level microarchitecture design specification for DSP and RISC processor subsystems. Proposed an 8-month design and verification schedule and executed to plan.- DSP: Area-optimised DSP design using VHDL. Manually translated Matlab model of the trajectory control algorithm of a photolithography machine's wafer handler module to an area-optimised VHDL DSP design. The end customer is a world leader in immersion photolithography systems.- Custom RISC processor design in VHDL.

Notable accomplishments:- Involved in the characterisation as well as development of high-quality characterisation solutions to ensure rapid tapeout of Altera's next-generation FPGAs.- VHDL design of a synchronous, ten-channel, user-programmable pattern generator used to characterise the performance of a (then) next-generation 28nm FPGA.- Custom RISC processor design in VHDL, complying with a subset of the SCPI instruction set.- Protocol designs: UART I2C, SMBUS in VHDL.- BiST / DFT designs: VHDL BiST circuits for on-chip temperature sensor and voltage regulator.

Notable accomplishments:- Tested VHDL / Verilog parser for a new Java-based CAD software used for seeding (automated pin placements) of FPGA designs.- Worked on several projects involving the use of Java, C, C++, HTML, and Javascript.

Sg

Wrote custom Matlab code to perform real-time signals acquisition and processing for a customer request. Conducted product trainings in Quanser and SigLab to several customers from the industry and academia.

M.Eng.Sc. (By Research), Microelectronics And Video Engineering

Bachelor Of Engineering (B.Eng.), Electronics And Electrical Engineering

Btec Higher National Diploma, Electrical And Electronics Engineering