Daniel Kho, Smieee Email & Phone Number

Singapore

Mukim 18 Tanjung Tokong, Penang, MY

- Chief Architect, Digital and AMS Full Chip Design- Architect, Video and Digital Signal Processing- Architect, Serial and Wireless CommunicationsProduct Development------------------------- Led the development of a video processor IP core.- Led the integration of AI core.- Led the development of communications IP cores: FFT, QPSK/QAM, MIPI C-PHY..

Singapore, Singapore, SG

- Involved in ASIC-FPGA co-design and co-simulation flows.- First to enhance existing ASIC functional simulation flow to support FPGA functional simulations.

- Responsible as company-wide Lead Engineer for several design service projects.- Responsible as Principal Trainer for technical training programmes.- Provided consulting, training, and design services to customers in areas of FPGA, IC Design, and DSP. Trained digital engineers in VHDL, Verilog, SystemVerilog, and UVM.- Appointed Consultant Trainer to.

- Founder of a small sole-proprietorship, Tauhop Solutions.- Responsible as consulting engineer for technical training programmes.- Provided consulting, training, and design services to customers in areas of FPGA, IC Design, and DSP. Trained digital engineers in VHDL, Verilog, SystemVerilog, and UVM.- Appointed FPGA architect for a marine electronics.

Chicago, IL, US

Notable accomplishments:- Involved in a mission-critical and safety-critical telecommunications basestation design project.- Bus protocol design: First to introduce synthesisable BFM technique, and VHDL Interfaces (record ports) technique for bus protocol design. Designed bus protocols for AXI, Avalon, and SPI using these VHDL techniques.- DSP: temperature.

Tempe, Arizona, US

Notable accomplishments:- Involved in FPGA chip microarchitecture definition for a safety-critical precision motion control system. Written a block-level microarchitecture design specification for DSP and RISC processor subsystems. Proposed an 8-month design and verification schedule and executed to plan.- DSP: Area-optimised DSP design using VHDL..

Notable accomplishments:- Involved in the characterisation as well as development of high-quality characterisation solutions to ensure rapid tapeout of Altera's next-generation FPGAs.- VHDL design of a synchronous, ten-channel, user-programmable pattern generator used to characterise the performance of a (then) next-generation 28nm FPGA.- Custom RISC.

Notable accomplishments:- Tested VHDL / Verilog parser for a new Java-based CAD software used for seeding (automated pin placements) of FPGA designs.- Worked on several projects involving the use of Java, C, C++, HTML, and Javascript.

SG

Wrote custom Matlab code to perform real-time signals acquisition and processing for a customer request. Conducted product trainings in Quanser and SigLab to several customers from the industry and academia.

M.Eng.Sc. (By Research), Microelectronics And Video Engineering

Bachelor Of Engineering (B.Eng.), Electronics And Electrical Engineering

Btec Higher National Diploma, Electrical And Electronics Engineering