Digital Design Engineer
CurrentWorking in Backend digital design P-core CPU team .I have worked on partition and block level design synthesis using synopsys Fusion compiler regression trials on clock with all possible test case to help deciding best mode of work to achieve best average latency without degradation timing and gain power.Worked on timing report analysis,Timing closer and signoff of block and partition. worked on logic equivalence check(FEV) from RTL to layout, power… Show more Working in Backend digital design P-core CPU team .I have worked on partition and block level design synthesis using synopsys Fusion compiler regression trials on clock with all possible test case to help deciding best mode of work to achieve best average latency without degradation timing and gain power.Worked on timing report analysis,Timing closer and signoff of block and partition. worked on logic equivalence check(FEV) from RTL to layout, power (ptpx),pdapWorked on pt_eco on different recipes to fix timing,power and transition Show less