Utkarsh Vij Email & Phone Number

8 years of rich experience in PD and STA on timing & congestion critical designs with 10+ successfull tapeouts of premium tier chips spanning across multiple advanced tech nodes (10nm, 7nm , 5nm, 4nm and 3nm) across TSMC and Samsung foundaries. Joined Cadence Design Systems recently . Will be working on Tempus mainly.Initially worked on multi power domain designs as Physical design engineer and later moved to STA role .Timing closure full chip hierarchical partitions having 40 plus million gates with very high logic depth and congestion prone designs .Involved in setting up STA flows and leading a team of 5-7 membersVivid experience of working with cross-functional teams spread across different geographies and time zones (EU, US etc)Specialties:Identifying the best & feasible solution on the fly for any issue that arises.Predicting the critical issues upfront & ensuring a smooth signoff along with achieving the best possible PPA's for any given design.Extending help to cross functional teams as & when required on top of meeting the existing responsibilities.Making sure of maintaining a healthy work environment in the team by creating open culture.Tools worked on:Floorplanning - InnovusPnR - Innovus/ICC2Sign Off tools - Primetime/Tempus

Listed skills include Microsoft Office, Microsoft Excel, Management, Customer Service, and 8 others.

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  Motilal Nehru National Institute Of Technology

  Electronics And Communications Engineering