* Responsible for the verification of high bandwidth Shared Local Memory (SLM) dynamically shared with L1 cache with normal write, partial write, atomic write and atomic write with read return features.* Participate in brainstorming sessions to define the efficient verification approach, test-bench architecture and methodology (UVM) used in the verification of Load Shared Cache cluster (LSC) blocks and its sub-blocks.* Complete the verification planning, test-planning and spec review for Shared Local Memory (SLM) block.* Create parameterized and reusable test-bench architecture for Shared Local Memory (SLM) in SystemVerilogusing verification methodology-UVM from scratch.* Code SLM model and scoreboard from the scratch to verify the correctness of the design.* Create UVM test classes and sequence classes to verify the design and all features defined as per design spec.* Manage the design and verification database for LSC blocks and its sub-blocks.* Serving as a hardware key contact person for the team of 30 people.Achievements:* Despite not coming from graphics background, I quickly ramped up, understood the spec, owned and developed the block level testbench from the scratch, verifying all the features in time.* Received four “intel appreciation awards” for completing the verification of SLM block in time with high quality.

* Verification environment for YAPP Router using SystemVerilog following UVM.* Completed labs to create an UVM agent, test classes, sequence classes for YAPP router.* Updated scoreboard to verify the behavior of the design.