Venkat Nithish Kumar Allu Email & Phone Number

Chicago, IL, US

• Development of Analog and Mixed Signal Circuits for high speed and high accuracy for DDR memoryinterface.
• Creating detailed validation and simulation plan including corner cases for the transmitter and Deskewblock
• Running POLO circuit simulations for performance verification and validate top level integration.
• Responsible for running reliability analysis and STA (using Primetime and siliconsmart) for the transmitter block.
• Generate all relevant circuit views for complex design like verilog A model, timing views.
• Review the MSV test plan and cover all aspects of circuit validation including DFX, functional, power management modes.

Chicago, Illinois, United States

• Designing interior parts such as Meter visor Cover, Console side panels, console bin, duct etc. in accordance with customer Requirements by using customer specifications and identify the Packaging Issues and bring them.
• Participates in Preparing the Design presentations for Design Reviews and interacting with Customer for Feedback.
• Working as a Team, Designing the Components based on Criteria Sections to meet Manufacturing requirements and Developing Detailed 2D drawings and applied GD&T concept to the design and BOM’S for the Designed parts.
• Designed the part as per the Design Standards and Collaborate with Production & other Engineering groups to eliminate problems, improve productivity and decrease cost.

Mysore, Karnataka, India

• Architected the block level structure for the design
• Implemented RTL using Verilog HDL Architected the class based verification environment using System Verilog
• Verified the RTL model using System Verilog
• Generated functional and code coverage for RTL verification Synthesized the design

India

• Worked on x86 Microarchitectural Core related bugs having strong debugging skills and triaging.
• Reviewed Architecture specification to root cause the RTL bugs.
• Inspect the regression failure, root cause the bug and creating a bug on the owner in JIRA platform
• Writing automatized triages in Perl to enhance the functional debug and triage process.
• Debugging in assembly language using Verdi