I'm a passionate techie who finds immense joy in crafting chips through hands-on implementation using EDA tools.I have a hands-on expertise in ASIC physical design, adept at managing block-level designs across the entire RTL to GDSII flow. This encompasses synthesis, floorplanning, power planning, CTS, PnR, extraction, STA, logical equivalence, and thorough validation with DRC/LVS and antenna checks.Tool Expertise:- Innovus, Tempus, Genus, Voltus, Conformal, Calibre, ICC2, DC compiler, PrimeTime, Xilinx-vivado.