Van Le Email & Phone Number

United States

Santa Clara, Ca, Us

Santa Clara, Ca, Us

Worked with cross-functional team from EPI, Process Integration, Device, Technology, Quality, Reliability, Apps, Marketing, and Supply Chain to build, test, characterize, and qualify our 700V and 1200V family of Vertical GaN semiconductors.Achievements• Led the development of a JMP data processing tool that quickly create yield reports, charts, wafer maps, variants yield table and trained the yield team on how to use it.• Helped to improve our manufacturability and yield, which resulted in yield greater than 90% from less than 20%.• Successfully got our 700V 1Ω part to max out the ESD tester and pass at 8kV.• Executed various Quals on our 700V 1Ω part and got it to pass HTGB, IOL, DHTOL, bHAST, and all the various Package Qual (i.e. Temp Cycle, HTSL, etc.).• Developed a full production suite of tests on the Keysight B1506A Power Device Analyzer for bench characterization.• Performed failure analysis (FA) on ESD, HTRB, HTGB, IOL, DHTOL, and H3TRB failures using Optical and Lock-In Thermography (LIT) to isolate failures and help improve our designs and processes.

Itasca, Illinois, Us

Joined as part of the Audience acquisition. Collaborated with cross-functional team to integrate Audience’s Operations processes (i.e. fab, assembly, sort, test, BOM routing, NPI planning, Qualification, and MFG documentation) into Knowles and trained Audience’s manufacturing flow to Knowles’ supply chain team. Developed Project schedules and ensure they either hit or exceeded deadline dates.Achievements• Released Knowles first Audio Edge Processor to Production for both a top tier1 mobile customer and a top tier1 social network customer. o Designed die level RDL to bring bond pads to all four sides so die could be packaged in a QFN, BGA, or eWLB package. o Designed eWLB in 2L instead of 4L and reduced the cost by 25%. o Root caused customer returns from poor DFT test coverage on ATE and at system level and helped to develop new functional test vectors and improved outgoing quality.• Analyzed WAT and yield data and resolved a SRAM leakage issue with FA that stabilized the memory yield and increased the overall yield by 11%.• Root caused a tester PMU glitch issue that caused a random eFuse bit to be blown by confirming the blown bit with delayering and SEM.

Mountain View, Ca, Us

Established and implemented processes for NPI bring-up, debug, test characterization, qualification, and production release to multiple OSATs. Built close relationships with key contacts at fab foundries, CMs and OSATs to communicate and effectively resolve problems.Achievements• First engineer in Operations covering product, test, and qualification roles and released Audience first in-house audio processor design to Production that sold 60+ million units to a top tier American cell phone customer. o Optimized assembly, wafer sort, and final test MFG flow and exceeded yield and cost targets. This generated 96M in revenue for Audience and allowed it to go IPO.• Released and supported 3 generations of audio processors and 2 generations of CODECs to the largest Korean cell phone manufacturer. o Root caused WLCSP RMA units that failed due to sidewall cracks with FA, which lead to an optimized laser groove profile, sawing speed, blade size and reached their Quality goal of zero defect.• Wrote the Test, Characterization, Reliability and Package Qualification plans for 8 products and successfully qualified them all for high-volume Production.

Ch

• Test program development on ATE ( (Verigy 93K & Credence Quartet) for Digital & Mixed-Signal ICs• Hardware design to test Digital & Mixed-Signal ICs on ATE• C/C++• UNIX, LINUX, Windows, & DOS• Test Cost Reduction• Quality & Yield Improvement• Release New Products to Manufacturing

Eindhoven, Noord-Brabant, Nl

Note: NXP is a spin-off from Philips Semiconductors.•Hardware Design•Test Program Development•Debug & Characterization•Quality & Yield Improvement•Release New Products to Manufacturing•Documentation (Word, Excel, Project, etc.)•Tutor & Train Junior Engineers/Technician

Eindhoven, Noord-Brabant, Nl

Key areas of responsibility• Test program and hardware development of assigned products from proto to production. Product types include Digital & Mixed-Signal ASIC; ARM cores, PLL, Flash, LDO, FM, Bluetooth, Baseband, RF, USB, UWB, PMU, Crystal Oscillator and GPS IP blocks for SoC.• Support New Product Introduction (NPI) to manufacturing.• Wafer sort and final test low yield analysis and improvements of assigned products.• Improve product quality through customer returns Level I analysis (i.e. RMAs) and customer product problem resolution.• Promote and implement cost reduction measures of assigned products improving product margin to target cost objectives.• Write Electrical Test Specification (ETS) for assigned products.• Support Technology Center and Business Line design engineers with assigned products and test issues.• Write scripts used to convert DFT-based outputs of JTAG, BSCAN, SCAN, BIST, and other functional simulations to tester vector using TASS and ATPG tools.Achievements• Led and delivered a USB test program development project for an octal-site on package test for the 93K with the Singapore and Philippines sites. The result was an 75% test cost reduction• Developed a scheme to test either on the digital or analog tester for DACs and ADCs for cable modem and set-top box.• First in our TPE group to use the master file concept for test program development on the 93K, which makes the program more modular and helps to reduce the test time with concurrent testing• Led and delivered a test program co-development project for a dual-site 2-die solution (USB & PMU) on the 93K with the Nijmegen, Singapore, and Philippines sites.• Successfully developed a hardware and software solution for an ASIC with 16 10-bit DACs.• Tutored and trained junior engineers, technicians and operators.

Key areas of responsibility• Coordinate with foundries and test vendors in test program correlation and qualification.• Release production test programs at offshore test vendors.• Generate various processes/specifications needed to support product in production.• Collaborate with internal engineering teams to drive and resolve process, test and customer issues.• Identify major failure modes, analyze fail signatures, and propose process/test changes to enhance yield.• Reduce cost through test time reduction and yield enhancement.• Set cost and yield targets for various products.Achievements• Discovered that Aspen NPU final test low yield at offshore site was due to damage caused to load boards by operators. Yield increased by 19% after the boards were repaired.• Found that Diamond NPU laser repair wasn’t done correctly at offshore site because system environment caused incorrect data in repair file. Yield increased by 15% after fix.

Eindhoven, Noord-Brabant, Nl

Note: VLSI was acquired by Philips.Achievements:• Delivered multiple ASICs to a company in Cupertino under an iconic founder, including a ramp up from prototype to 1 million units shipped in 90 days. This helped the company delivered its products to the consumers on time and our BU the top revenue producer with 250M and top revenue product for the company.• Analyzed PCM data from FAB and tightened process parameters to help get higher speed chips for the company in Cupertino. This increased revenue and profit margin since these chips have higher ASP.• Qualified and improved 0.2um process for foundry FABs.• Collaborated with Process Engineers from FAB to qualify a new process flow when passivation cracking was found in the 0.35um process. It increased the yield by 10% for all products on this process.• Discovered an incorrect old I/O library used in the META chip design and alerted the cell development group of the problem. This saved about $1 Mil dollars from creating a useless mask set.• Worked with assembly engineers to qualify IBM gold bumping process.• Discovered DRC violations in ARCUS design as well as a design flaw where a floating gate was repeatedly used in the design, which cause excessive high current leakage. This resulted in a saving of a few hundred thousand dollars from building useless Engineering samples.• Discovered a race condition in a design, which caused the part to fail at high temperature and voltage.• Inherited a low yielding ASIC from a senior engineer and increased the yield from less than 15% to over 80%.• Took the initiative to implement and sustain productivity tools in the UNIX environment. This significantly helped to speed up test program development for our group by 20%.

Education record

Bs, Electrical & Electronic Engineering