Varduhi Julhakyan Email and Phone Number
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Release Verification and Validation Management: Responsible for planning and managing the release verification and validation processes for Electronic Design Automation (EDA) tools, ensuring high-quality product development and compliance to industry standards.Verification Framework Development: Skilled in developing and enhancing verification frameworks with a focus on integration and automation. Optimizing verification processes to improve efficiency and reliability in technology solutions.Engineering Team Development: Dedicated to cultivating strong engineering teams by sharing knowledge, mentoring, and promoting corporate values.Cross-Cultural Collaboration: Capable of effectively collaborating with multi-cultural and multi-disciplinary teams.
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Team Lead Manager, Formal Verification Tool QaInstigate Design Mar 2022 - PresentLead Manager of Formal Verification Tool Testing TeamKey Responsibilities:- Develop and maintain an automated verification system that implements flow for each FPGA vendor, ensuring formal equivalence checking of intermediate netlists.- Direct the creation of a verification suite, including failure analysis to identify and troubleshoot issues effectively.- Manage bug reporting processes to FPGA vendors, ensuring continuous improvement of the verification tools. -
Lead Engineer, Ai Algorithm Acceleration On FpgaInstigate Design 2018 - 2020Led research and development efforts to accelerate AI software algorithms using FPGA technology. Focused on optimizing algorithm performance through parallelization and hardware/software co-design.Key Responsibilities:- Conducted in-depth analysis of AI algorithms and FPGA architectures to identify opportunities for acceleration and optimization.- Defined the architecture for hardware/software co-execution systems to maximize performance and efficiency.- Adapted software implementations to align with High-Level Synthesis (HLS) tool requirements, ensuring compatibility and performance.- Developed and implemented a performance benchmarking environment to evaluate and validate system performance during development. -
Team Lead Manager, Fpga Architecture VerificationInstigate Design Nov 2017 - 2018Led a team focused on the verification of Network-on-Chip (NoC) designs implemented on FPGA platforms. Oversaw the testing and performance evaluation of NoC prototypes to ensure functionality and performance.Key Responsibilities:- Managed the verification process for NoC design prototypes on FPGA, ensuring accurate implementation and compliance with design specifications.- Conducted performance analysis of NoC models loaded into FPGA clusters to assess efficiency, throughput, and latency. -
Team Lead Manager, Fpga Tool Vendor Release SupportInstigate Design 2013 - 2017Led a team managing the release process of the FPGA development kit, including planning, verification, and packaging. Coordinated efforts to ensure high-quality releases and effective customer support.Key Responsibilities:- Oversaw release planning activities based on feedback and reports from the vendor's customer support team to align with user needs and priorities.- Directed the verification and validation processes to ensure that releases met quality standards and functional requirements.- Managed the final stages of release packaging, including automation of release package creation and documentation validation for the release, ensuring they were complete and error-free.- Conducted benchmarking of Place and Route (PnR) processes to assess and optimize performance and efficiency. -
Lead Engineer, Tech Writing Automation And Tool Tutorial DevelopmentInstigate Design 2012 - 2013Developed and automated technical writing and tutorial content generation using advanced toolsets. Focused on streamlining documentation processes and enhancing user guidance through automated solutions.Key Responsibilities:- Utilized the Instigate Application Framework 2.x to automate technical writing processes, improving efficiency and consistency in documentation.- Designed and implemented Proximus tutorial content, leveraging automated tech writing tools to structure and generate user guides and instructional materials. -
Lead Engineer And Manager, Qa Of Static Timing AnalyzerInstigate Design 2011 - 2012Led a team responsible for quality assurance of static timing analysis (STA) tools. Focused on developing TCL command lines, creating test plans, and verifying STA tool functionality to ensure accuracy.Key Responsibilities:- Developed and optimized TCL command line for the STA tool using Instigate Application Framework 2.x, enhancing tool functionality and usability.- Created test plans to evaluate the STA tool’s accuracy, ensuring thorough testing coverage.- Oversaw the verification process for the static timing analyzer, identifying and addressing issues to ensure the tool met all quality standards. -
Manager, Ae/Qa/R&D Teams For Proximus Hdl ExporterInstigate Design Cjsc Oct 2008 - 2011Managed cross-functional teams in Research & Development (R&D), Application Engineering (AE) and Quality Assurance (QA) for the Proximus HDL exporter project. Led efforts in developing and verifying HDL exporting systems and enhancing the Proximus library.Key Responsibilities:- Developed and optimized the Proximus Verilog exporter.- Led the development of various components within the Proximus library, including: * Arithmetic Template Library for Scalars * Matrix Template Library- Managed the development of a Network-on-Chip (NoC) system using the Proximus library, ensuring efficient design and integration.- Led the verification of synthesizability for exported HDL to confirm compatibility across different synthesis tools.- Led the development and maintenance of the Proximus Verification Environment. -
Eda Tool Verification EngineerInstigate Cjsc Feb 2007 - Dec 2008Key Responsibilities:- Designed and implemented an automated testing environment using TCL and Bash, enhancing testing efficiency and accuracy.- Verified simulators and hardware debuggers for a massively parallel proprietary system, ensuring robustness and reliability.- Maintained and updated existing test suites to align with evolving system requirements and improve test coverage.- Verified and validated the syntax and functionality of simulator commands to ensure proper execution and accuracy. -
Software EngineerInstigate Cjsc Jul 2006 - Feb 2007Key Responsibilities:- Designed and developed a UniPro model using ESL design techniques.- Created a verification environment for RTL synthesis, simulation, and verification, ensuring accuracy and efficiency of testing processes.- Conducted synthesizability analysis to address issues within the UniPro model, optimizing it for successful synthesis and deployment. -
LecturerSeua Gyumri Branch Sep 2008 - May 2012Key Responsibilities:Training Delivery: Conducted lectures and laboratory sessions focused on CPU architecture, delivering in-depth knowledge and practical insights to students.Curriculum Development: Developed and refined course materials and training content to align with educational standards and industry requirements.Student Engagement: Fostered a collaborative learning environment, providing guidance and support to students to enhance their understanding of CPU architecture concepts.
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LecturerGitc Feb 2008 - Dec 2010Key Responsibilities:Course Delivery: Delivered lectures and practical training on various advanced topics, including:CPU Architecture: Provided in-depth knowledge on CPU design and functionality.ESL Design Flow: Taught methodologies and workflows for Electronic System Level (ESL) design.SystemC: Instructed on the use of SystemC for system-level modeling and design.Proximus: Educated on Proximus tools and techniques (ensure relevance or provide more context if necessary).Build Process and Automation: Covered best practices in software build processes and automation techniques.Training Materials Development: Developed and maintained training materials and course content to ensure relevance and accuracy.Student Support: Engaged with students to address questions, provide feedback, and support their learning journey.
Varduhi Julhakyan Skills
Varduhi Julhakyan Education Details
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GitcHw/Sw Development -
Cisco Networking AcademyNetworking -
State Engineering University Of ArmeniaAutomation Of The Industrial Processes
Frequently Asked Questions about Varduhi Julhakyan
What company does Varduhi Julhakyan work for?
Varduhi Julhakyan works for Instigate Design
What is Varduhi Julhakyan's role at the current company?
Varduhi Julhakyan's current role is Team Lead Manager at Instigate Design.
What is Varduhi Julhakyan's email address?
Varduhi Julhakyan's email address is va****@****ail.com
What schools did Varduhi Julhakyan attend?
Varduhi Julhakyan attended Gitc, Cisco Networking Academy, State Engineering University Of Armenia.
What are some of Varduhi Julhakyan's interests?
Varduhi Julhakyan has interest in Intelectual Games, What? Where? When.
What skills is Varduhi Julhakyan known for?
Varduhi Julhakyan has skills like Linux, Tcl, C++, Qt, Subversion, Oop, Shell Scripting, Verilog, C/c++ Stl, Fpga, Gnu Make, Design Patterns.
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