Varun Mathur Email & Phone Number

Austin, Tx, Us

Santa Clara, California, Us

Focusing on critical path analysis of next gen server products. Once critical paths are identified, work with design to reduce path delay, thereby potentially increasing core frequency and product performance.

Santa Clara, California, Us

Managed P5000/C5000 SOCs for networking & security appliances and next gen SOCs for satisfying the exploding processing needs at the network edge.• Devising benchmarking strategy based on research of targeted market segments.• Devising SKU stack for the product based on customer demand & requirements, engineering viability and yield expectations.• Sitting in on pricing discussions with pricing team and senior directors, providing product inputs.• Evangelizing the product to different business segments for their adoption, to executive leadership team for their continued support and to sales teams worldwide for creating customer awareness and interest.• Being the voice of the customer and business in program execution meetings comprising of the whole engineering team, providing list of features to be worked on and priority.• Presenting the business case for the product to engineering teams for any proposed changes to feature list or priority.• Regularly facing customers to keep them engaged and interested in the product, ensuring their concerns are heard and resolved in a timely manner.• Actively engaged with manufacturing by providing short (8 Quarters) and long-term demand signals (5yrs), driving yield improvement and cost reduction activities, and ensuring sufficient supply for customers.• Spearheading product launch planning with marketing, PR, sales, legal, IT, logistics and external design agency.• Coordinating and planning the fabrication of samples (MVP) for customers to try out, deciding quantity per customer and associated logistics.

Santa Clara, California, Us

Leading Burn-in (stress) test program development on 10nm server products.

Santa Clara, California, Us

Stress 10 & 14 nanometer server microprocessors (datacenters) at elevated voltage & temperature to ensure quality/reliability at the customer. Drove 2 products from NPI to HVM.• Customizable Burn-in (BI) ATE test program (TP) development, implementation and NPI to HVM support. • Revamped BI TP to handle parallel stressing and data logging of dies on complex multi-chip per package (MCP) products.

Santa Clara, California, Us

Developed ATE test programs for wafer sorting, post-packaging test and frequency binning of 10/14nm client microprocessors. Drove four 14nm products from NPI to HVM.• Championed shift left by introducing innovative data driven tests earlier in the testing flow.• Spearheaded cross team effort to enable delay-optimized high quality DFT content at first silicon (NPI) to meet key product milestones with high confidence. • Reduced 50% test time by removing patterns/tests, proved ineffective through volume data analysis.• Drove 2 products to cold temperature test elimination post packaging, reducing 10% cost.• Streamlined qualification process of releasing changes to test programs cutting down 60 man hours of redundant work per month.• Gained utmost trust of Fab/Technology development stakeholders by root-causing multiple high priority yield sightings and driving corrective measures in the test program.• Trained Factory engineers/technicians on test program deployment and troubleshooting. • Mentored peers on data presentation skills to influence Fab/Factory stakeholders for moving tests to kill.

Santa Clara, California, Us

Worked in the SCAN DFT team on Pre Si verification of Graphics/ Display IP. Responsibilities included -• Formulating the test plan with the micro-architect and SCAN unit owner.• Creating and enhancing existing tests/ System Verilog checkers and automation files.• Running weekly regressions and making updates to tests to keep up with design changes.• Debugging failures, finding/reporting RTL bugs/ test issues and driving fixes.• Writing, maintaining and enhancing test generation scripts in Perl.• Developing tests for Gate Level Schematic models to ensure functionality of the unit delay gate level netlist.• Validating ATPG tests on the GLS model to ensure health of model and find netlist issues/ test issues/ ATPG flow issues.

Shelton, Ct, Us

Designed clock multiplier(clock doubler and tripler) circuits, wrote their verilog codes, synthesized them on a Spartan x3cs700AN FPGA using Xilinx ISE design suite-11 and tested the performance of the circuits using an oscilloscope.

New Delhi, New Delhi, In

Studied basics of Satellite Communication, worked on a project to provide Voice & Data connectivity through Satellite Network to remote and inaccessible villages in India. Presented a SEMINAR in the company as well as my university.

Masters, Electrical And Computer Engineering

Masters, Computer Engineering

Bachelor Of Technology - Btech, Electrical, Electronics And Communications Engineering