Over 18 years of experience in ASIC Design Verification, Pre-silicon Validation, Post Silicon validation & SoC Application Engineering.• Excellent hands on experience Module and SoC level test environment development. • Excellent hands on experience in Functional verification of RTL Modules using HVLs – System Verilog & Specman ‘e’.• Experienced in developing Verification environment in using Verification Methodologies like UVM, OVM & eRM.• RTL coding using HDLs – Verilog and VHDL • Experience in application verification & validation using quick turn / FPGA setup / post silicon validation• Creation of design documents and verification plans• Project feasibility study, planning, task break down & effort estimation .• Technical / Project management - Lead a big team of Engineers • Working with multi-cultural, multi-location design teams• Lead Verification CoE in MindtreeHandled Complex projects with First silicon Success.