Valeriu Codreanu Email & Phone Number

Amsterdam, North Holland, Netherlands

Amsterdam Area, Netherlands

- Led and grew SURF’s Machine Learning efforts.– Contributed to SURF’s National Competence Center (EuroCC) status.– Defined and started SURF's Machine Learning and GPU service desks.- Extended the SURF's research collaboration with Intel.– Actively contributed to technical work in projects and support.

Amsterdam Area, Netherlands

My main contributions in the Compute Services unit were:- Principal Investigator for Intel Parallel Computing Center and secured funding for research on ”Scaling out Deep Learning”. This activity started in 2017 and is ongoing. Current funding level is increasing, and our results have been widely publicised. This helped us start many national and.

Eindhoven Area, Netherlands

My research topics were mostly on developing and extending the CompSOC architecture to other computing architectures, such as the ARM v7-M. I have thus demonstrated that applications can be executed in a composable manner not only on the CompSOC FPGA hardware, but also on ARM Cortex M3/M4-based development boards. I have also developed a readline-based.

Groningen, Netherlands

My research topic was Automatic Parallelization of computer programs from their CPU sequential implementations to GPU-optimal ones. Besides working on the automatic parallelization toolkit, I have been involved in various other projects such as developing the first real-time affine-invariant feature extractor (GPU-ASIFT) and developing GPU-SVM, a versatile.

The PhD study involves creating an efficient parallel system that can make use of all types of parallelism(data-level, thread-level, instruction-level), and deliver the parallelism through automatic compiling optimization techniques.

I instructed 2nd and 3rd year Bachelor students, as well as Master students, the following topics: Digital Integrated Circuit Design, Computer Architecture, Cryptography Algorithms

Delft, The Netherlands

I was involved in the research of scheduling policies for a heterogeneous system comprising of an interleaved multi-threaded processor connected with a wide-vector co-processor. The system was implemented on a Xilinx Virtex-6 LX240T FPGA and various execution scenarios were measured.

My role in Vivaja Technologies was to coordinate the development of an object-oriented processor called ObjectCore. I was also involved in the development team of Vivaja. The Java implementation out-performed any embedded Java execution solution tested in terms of performance/area and performance/watt.

Bs & Ms, Electrical Engineering

Highschool, Mathematics-Computer Science