 Expertise in Formal Property Verification (FPV)• Signed-off on several IPs as individual contributor.• Ensured proper test-planning, properties and model coding, abstraction and RPD and coverage-based sign-off to achieve zero bug escape and shift-left. catching more than 100 bugs.• Conducted initial project breakdown to identify Formal Verification (FV) friendly DUTs (Design under Test) to ensure maximum FV QoV (Quality of Verification).• Deployed FPV to ensure not just functionality of IPs but also to ensure security aspect of such IPs.• Have worked on design related to CPU, Interconnects, Networking, etc., contributed to Intel’s 4th, 5th and 6th generation Xeon scalable processors. Expertise in Reactive formal• Reproduced bugs that landed in post silicon for better understanding of scenario and quicker resolution in span of few weeks, deploying advanced formal techniques and abstractions• Work involved discussion with several architects, micro-architects, designer to narrow down IPs to catch and reproduce the bug and verify workarounds and hardware fix. Team management and development• Technically led 3 teams of 5-10 formal verification engineers to formally signoff IPs involved in CPU, Interconnects, Networking, etc. catching more than 400 bugs.• Allocated and bifurcated task among project members and came up with strategies to ensure timely sign-off.• Trained around 50 engineers with basic and advanced concept of formal verification by coming up with lab exercises for practice and part of hiring team Contribution to FV literature• Authored 6 papers in span of 3 years winning best paper award in DVCON India 2022, and JUG India, 2024, 3 papers got selected for DAC USA, 2022, 2023, 2024 for poster and paper presentation.• Literature focused on FV methodologies for faster execution, zero bug escapes, shift-left, and addressing functional and security issues in IP.