I have the experience of taping out high performance chip in lower technology node working as a physical design engineer at block level which involves efficient floorplanning, placement , clock tree synthesis, timing optimization, routing, timing closure and physical verification closure.

I have worked on Analog circuit and layout design. I have designed level shifter block. The design includes both the circuit and layout design of the level shifter.I have worked on modelling the sub-blocks of Thermal sensor using Verilog-A modelling language. The blocks i modeled includes sense stage and sigma-delta ADC stage.