Venkat Rohit Koppana Email & Phone Number

• Played an active role in implementing new features, fixing bugs, code quality improvements, test framework improvements, debugging performance issues, and bring-up of features for high performance 5G BTS SoC.• Implemented packet capture feature at L2 layer by leveraging Hardware acceleration features.• Implemented QoS Feature to determine transmit queue using LPM tables to match against egress port, VLAN ID and PCP.• Contributed to features such as Green data-plane (a power-savings feature) and Multi-Service data-plane (an application-level differentiation of packet processing paths).• Implemented a proof-of-concept to measure and publish per core processing cycle count for all modules involved in packet processing.• Actively pursued learning exercises in Next-gen platform architecture, P4 SDK, Cloud Native tools for Networking, Containerization of existing packet processing stack and microservices.

Phoenix, Arizona, United States

• Played a crucial role in implementing platform software features and optimizations for an on-prem 5G Edge Compute platform that supports Time Sensitive Networking (TSN).• Optimized platform and software stack configuration for TSN reliability through appropriate thread prioritization, core pinning, interrupt isolation, driver customization and updates, and coding optimizations.• Played a lead role in containerizing RAN DU, CU, and CN (UPF, AMF, SMF) software stack and the build environment.• Contributed to significant improvements in reliability and performance of CU data-plane stack.• Implemented uplink traffic classification in User-endpoint, to prioritize TSN traffic over eMBB and time critical traffic.• Persistently pursued the goal of 99.999% reliability for E2E latency of TSN traffic.• Enabled strict priority queueing in Intel’s 700 series NICs to prioritize downlink TSN traffic over eMBB traffic, in N3 and F1 interfaces on CN and CU platforms, which significantly improved the reliability of TSN traffic under heavy network load.• Worked with NIC driver team to implement a custom filter in the NIC for bifurcating IP and PTP traffic between NIC’s PF and VF on Core Network’s N6 interface.• Implemented BPF filters in TSN Translator, a tool that supports IEEE 1588 Transparent Clock functionality on N6 interface, to prevent looping of broadcast traffic on N6 interface.• Implemented PTP sync monitor utility that monitors and publishes PTP sync status to DU control plane stack via Message Queues and Grafana Dashboard via Prometheus.• Improved PTP sync stability of 5G time domain and Network time domain to less than 1 micro-second jitter under heavy network load.• Enabled LTTng logging for containerized software stack and used LTTng kernel logging to debug platform and software stack stability, reliability, performance, and latency issues.• Used Jinja templating engine to generate configuration files for different platform configurations.

Phoenix, Arizona Area

• Involved in Wi-Fi driver integration, HAL API implementation, debugging and fixing critical Wi-Fi subsystem bugs, coordinating Wi-Fi validation and performance tests, and SDL activities for a Cable Modem Gateway platform.• Fixed critical Wi-Fi subsystem bugs and made significant contributions that helped in achieving release quality SDK for a key customer.• Reduced platform boot time by 50% by enabling early initialization of Wi-Fi subsystem and decoupling invalid subsystem dependencies.• Actively contributed to bug reduction and debugging Wi-Fi performance issues in cable modem platforms.

Sacramento, California Area

• Worked on enabling Intel® Optane™ Technology based storage and memory solutions for current and future Desktop/Mobile platforms running on Intel® Core™ Processors.• Collaborated with Software Architects and Firmware Engineers for optimizing power, performance and thermal profile of Intel® Optane™ memory modules used as storage accelerator.• Generated multiple patent ideas, with one patent currently pending

Tempe

Assisting the instructor in ‘Embedded Sytems Programming’ class, grading projects, holding office hours in the Embedded Systems Lab, monitoring discussion threads and assisting students in the lab.

• Developed test cases for stress testing of Intel Atom based platforms running Android.• Developed a tool using python and ADB for automating the validation process with a easy to use GUI based on wxPython.• Added support for Windows platforms to a performance analysis tool using PsTools suite and Intel SoC Watch tool.

Tempe

Developed embedded software applications on Intel Edison platform, under the guidance of Dr.Yann-Hang Lee

Chennai Area, India

•Involved in two major technical releases and contributed efficiently towards product development and stability by ensuring quality code deliveries.•Developed ‘Easy Installation’ feature, an automated provisioning systems for third-party SIP phones using TFTP and DHCP protocols.•Performed benchmarking and performance evaluation for a new 800 MHz processor (Freescale MPC8377) at different DDR clock speeds using tools like NBench, STREAM, UnixBench and OpenSSL.•Played a vital role in successfully upgrading the system from 667 MHz processor with 256 MB RAM to 800 MHz processor with 512 MB RAM.•Identified the system bottleneck and increased the scalability of VoIP application from 150 clients to 200 clients and performed profiling for the same.•Provided L3 support to customer sites through remote connections and provided workarounds whenever feasible. •Assisted application and validation teams in setting up test environment and gathering performance statistics.•Gained hands-on experience of working with a huge code base, SCM tools like IBM Rational ClearCase, ALM tools like ClearQuest, and open source software and build systems.

Master'S Degree, Computer Engineering

Post Graduate Diploma, Embedded Systems Design

Bachelor Of Technology, Electrical And Electronics Engineering