Venugopal M Email and Phone Number
Work experience:• Currently working on 100+Gbps PAM4 Serdes development.• Designed 32Gbps Transmitter that supports PCIe Gen5 through Gen1: A new architecture was developed to improve the deterministic Jitter of the Driver @32Gbps and is successfully proved in Silicon, and is • Built an Analog team of size ~13 designers starting all alone• Managed the team of ~5 engineers as part of the 25.6Gbps Serdes development• Design of 16nm FinFET based low jitter, highly monotonic 3.2GHz Digitally Controlled Ring Oscillator for the Digital PLL• Lead the analog development for Low Noise PCIe2.0 and USB compliant reference clock generation for the PCIe, USB PHYs and entire chip for an ASIC Chipo Interacted with the Customer from the development to the final GDSIIo Interacted with the third party Vendor during integration of PHYso Responsible for the Noise budgeting of the entire Clocking System to support PCIe and USB specifications• Designed the low phase noise output Clock Driver in Synthe-CLK-ADV product for Clocking Base-station Applications which outperformed our competitorso Interacted with Marketing/Apps/PD and PE groups during development to production of the producto Supported the Silicon validation, involved in multiple debugging• Designed a highly linear Differential Charge Pump for 12.5GHz PLL• Designed an Analog Equalizer in the Receiver Frontend for multi-protocol standards working upto 5.4Gbs• Designed the High Speed Clock Channel running at 16GHz for 28Gbps Serdes meeting very tight specifications for Noise and DCD• Designed the REFCLK right from the source to across the Chip span of <25mm for 28Gbps Tele/Data-com Serdes Applicationso Meets very tight noise specifications• Worked on Top level integration for 14.1GHz Hybrid PLL• Designed interfaces involving various Top level assembly blocks involving ESD, Packaging and Digital teams • Integrated top level Tx, Rx and Clock unit for 3.02Gbps SerDes.Specialties: Good knowledge of Analog and Mixed Signal fundamentals and good design skills of high speed analog Serdes design circuits like Transmitter, Equalizer, Clocking circuits with deep understanding of Jitter.
Micron Technology
View- Website:
- micron.com
- Employees:
- 20793
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Principal EngineerMicron Technology Jul 2021 - Present -
Manager - Mixed Signal DesignMicrochip Technology Inc. Apr 2021 - Jun 2021Bengaluru, Karnataka, India -
Principal, Mixed Signal Design GroupMicrosemi Corporation Apr 2019 - Mar 2021Bengaluru Area, India -
Staff Mixed Signal DesignerMicrosemi Corporation Mar 2017 - Apr 2019Bangalore -
Senior Mixed Signal Design EngineerPmc-Sierra/Microsemi Jan 2016 - Mar 2017Bangalore -
Mixed Signal Design Engineer - Level IiPmc-Sierra Jul 2010 - Dec 2015 -
Design EngineerSandisk Jan 2008 - Jan 2009I worked as a Design Engineer in ASIC Analog and Digital IP team at Sandisk
Venugopal M Education Details
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Vlsi-System Design -
Electrical, Electronics And Communications Engineering
Frequently Asked Questions about Venugopal M
What company does Venugopal M work for?
Venugopal M works for Micron Technology
What is Venugopal M's role at the current company?
Venugopal M's current role is Principal Engineer - Design Lead at Micron Technology.
What schools did Venugopal M attend?
Venugopal M attended National Institute Of Technology Warangal, Jawaharlal Nehru Technological University.
Who are Venugopal M's colleagues?
Venugopal M's colleagues are Louis Hong, Siril E Salin, Alan Hsu, Tracey Shults, Arun S., Krishna I, Muhammad Azrie Razale.
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Venugopal M
Bengaluru -
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