• Responsible of Synthesis and Place and Route flow for digital SERDES IP in 16nm.Timing constraints development, timing constraints validationParticipated in developing improvements to scripts/methodologies/flowsSignoff checks:o EMIR and power analysis with Voltuso DRC verificationo Static Timing Analysis and block-level timing closure with Tempuso Mixed signal STA between analog and digital• Verification of SERDES designSetup verification scripting environment based on pythonDevelopment of company UVM base classes and UVCso Clock and reset agentso Agent and environment base classesDevelopment of company assertion librariesDefined UVM verification methodology / coding guidelines for the teamDefined SVA verification methodology / coding guidelines for the team

• PLC (Power Line Communication) project :Verification of MAC part : Verification planning, UVM testbench development of sub modules, assertions and functional coverage implementation. Firmware oriented verification, C++ tests development and debuggingFormal property checking of arbiters, and bus bridges, control-oriented blocks. Linting and CDCPost-silicon debug, found issue discovered in FPGA and allowed faster debugging.Functional and structural coverage analysis. Assertions optimization for simulation performance and formal closure.First time silicon success in 40nm low power technology• MoCA (Multimedia over coaxial cable) project :Set up top level environment bench for Moca project including RAL mechanismsWriting of models for analog (wrappers, DPI C models) for mixed simulations (analog + digital)LDPC : Design of input/output controllers. Developed verification plan and verification environment using DPI, coverage closure : 98% coverageSet up FPGA environment, for benchmarking (pattern generation + noise generation + monitor)Traced plot PER =f(SNR) with different max iteration number • G.Hn standard project, collaborating with Marvell Spain :Verification plan and formal property checking of DMA block, developed functional coverageOptimization of FEC decoder path, decreased area by 11% and 2x throughput, design and verificationOptimization of FEC encoder for clock frequency increase• FM radio stand-alone project :Verification Lead roleDeveloped top verification plan, delivered clear regression status to top managementDFT LBIST design (custom interface block) and top-level verificationGate level simulation in slow, fast and typ corners, and power analysis support (VCD dump)• NFC stand-alone project:Debug UPF gate level simulation and reported power isolation issues to backend teamDFT : top level simulation and support to lab teamVerification : DPI import of RX chain, delivered and analyzed coverage report, regression status

• Developed SVA Assertions and functional coverage• Verification Planning from design specifications• Applied formal property checking closure with advanced techniques : cutpoints, semi-formal, constraint design state-space• Assertion optimization for simulation and formal• Verification of PLC MAC scheduler and memory controllers with formal property checking, allowed to find bugs deep hidden in the design.• Applied formal techniques for : post-silicon debug, property checking, CDC