Chief Technology Officer
CurrentBased on two decades of electronic hardware design experience in low-level and highly efficient systems, I developed a state of the art Generative AI hardware accelerator, which pushes the limits of technology, by getting ever closer to the mathematical limits of AI algorithms. The technology is proven and its performance measured in several FPGA families using popular LLMs, where we provide above 20% more efficiency than top competitors, such as Nvidia and Google. This efficiency translates in a higher speed, lower power, and a smaller size, using the same base technology.My role at RaiderChip involves managing the engineering team, oversee the core technology development, and handle strategic hiring to build our capabilities.I lead the engineering efforts to target our technology from low-cost FPGAs up to semiconductor ASIC SoCs to serve users at large scale, as well as supporting the latest Generative AI LLMs, such as the Phi family from Microsoft, the Llama models from Meta, and its many derivatives, as well as the much larger enterprise level LLMs.
