Vignesh R. Email & Phone Number

Cupertino, California, Us

West Lafayette, In, Us

Lab Instructor for ECE270 - Intro to Digital System Design course.Key Responsibilities -- Manage two 3hr Lab sessions every week (30+ students per session).- Hold office hours (3hrs) every week to clarify doubts, verify pre-labs and makeup labs.- Proctor Exams and weekly Quizzes.- Overview of the Lab Experiment (Presentation).- Coordinate with the UTAs for the lab session and lab practical exam.- Assist students with check-off and debug circuits.- Grade and maintain student HWs and Lab records.

Santa Clara, California, Us

Designing and Integrating key features and implementing bug fixes in next generation ECC IP.

West Lafayette, In, Us

Grading weekly Homeworks for ECE 202 Linear Circuit Analysis II (~100 students).

West Lafayette, In, Us

Grading weekly Homeworks for ECE 202 Linear Circuit Analysis II (~60 students).

Palo Alto, California, Us

SoC Verification of Proprietary Timer IP.• Ramp-up on IP features from IP Specification.• Identify Integration scenarios to verify.• Update Test Plan and Review with Designer.• Responsible for Regression Clean up on IP.• File + Track Bugs and Verify Bug fixes on IP/FE.SoC Verification of Display Controller Subsystem.• Identify Integration and Functional scenarios to verify.• File + Track Bugs and Verify Bug fixes on integration and/or functionality.• Work closely with the design integration team for the bug fixes and closure.• Support Validation team in developing system level environment based on SoC level verification environment for Display subsystem.• Develop scripts for the Data Integrity flow and checks for SoC and Block level simulations.Block level Verification of BT656 block in Display Controller Subsystem.• Develop UVM Monitor for BT656 interface specification.• Integrate the UVM Component with Display Block level Environment.• Verify the various functional scenarios.

Geneva, Switzerland, Ch

CUT- ISimplest Automotive SoC for Park Assist Applications.SoC Verification of Device Censorship and Security IPs.• Overview on Automotive SoC and TB Environment.• Ramp-up on IP features from IP block guide.• Update Verification plan for IP in Enterprise Planner.• Clean up Make errors and Link errors in regression.• Debug + Track regression failures with FE/TB Release.• File + Track Defects in IP/FE/TB. Verify fix for the Defect.• Debug failures in zero delay simulations at gate level netlist.• Debug failures and violations in gate level netlist with SDF - Worst corner.CUT - IIMulti-million gate Automotive SoC for PowerTrain Applications.SoC Verification of Device Censorship and Security IPs.• Update Verification plan for IP in Enterprise Planner.• Develop tests to verify the Change Requests implemented in CUT-II.• Clean up Make errors and Link errors in regression.• Debug + Track regression failures with FE/TB Release.• File + Track Defects in IP/FE/TB. Verify fix for the Defect.

Palo Alto, California, Us

TAPEOUT- I• C-based Verification of IP Integration in Subsystem and SoC.• Register Read-Only Regression Cleanup.• Toggle Coverage Analysis in IMC tool.• Connectivity Checks in JASPER.• Gate Level Simulations Debug in Unit-delay Power and Ground Netlist.• Gate Level Simulations Debug in SS- and FF-corner Power and Ground Netlist.

Bengaluru, Karnataka, In

• Active SIM based Call Log Module.

Master’S Degree, Electrical And Computer Engineering

Bachelor Of Technology (B.Tech.), Electrical And Electronics Engineering

All India Senior School Certificate Examination, 2009, Mathematics And Computer Science

All India Secondary School Examination, 2007