13+ Years of expertise in physical design of Cutting-Edge SoCs. As a seasoned professional, I have dedicated over a decade to the intricate world of Physical Design Verification & other signoff domains such as PDNA, RDL, IO-Padring, floorplan and methodology/Automation. My journey spans across complex SOC projects, where I’ve meticulously ensured the integrity and functionality of these advanced semiconductor devices.I have been part of recruitment and training process. I trained & mentored engineers on Physical verification. I Managed and motivated project teams to promoted collaboration and keepmembers on-task and productive.I’m Proficient at EDA tools such as Synopsys - ICC/FC, Innovus and Calibre. Expert & highly skilled on all the latest tech nodes of different foundries.