o Own pre-silicon and post silicon activities for BIST content for production and characterization.o Responsible for ATE test program and pattern development (via origen sdk), rtl simulations to check pattern readiness and interface with verification team to come up with test sequences for pattern development.o Perform data analysis on test data and present to test and product team to drive improvements.o Mentored new hire test engineer and Intern to come up to speed with NXP processes and test activities.

ATE program owner for dGPU - SW Infrastructure setup; Integration; Standardization

Test Chip ATE Test Lead; Probe Test; Final Test; First Silicon Bring-up; Production test; IP characterization; Reliability Studies; ATE capacity & configuration; DIB design re-use; 93K platform

- ATE Test Program Lead (Verigy/93K) for 20 nm, 16 nm finfet node Test Chips; Wafer Sort, Final Test. * Test HW decisions and ATE configuration owner for wafer and package test. * First Si bring-up, debug, characterization - SCAN, SRAM BIST, RO, Test Transistor structures * Create Bump mapping for ATE. * Influence substrate design for re-use of ATE HW to align to one single package type for test chips- Extensive collaboration with yield engineering to ensure minimum time to data.- Interface with fab/subcons for closing ATE capacity and HTOL requirements.- Always working on next generation process node for drive to yield test chip vehicles(20 nm, 16 ff)

Principal responsibility of delivering production and characterization program for Freescale's network processor; In-depth debug on VERIGY 93K, VERIGY 93K Classic Test Method development;Production support - yield improvement, test time reduction, multisite program conversion

Leading test engineering efforts from India Design center to support next gen QorIQ products.- Responsible for leading the India team to deliver simulated production and engineering patterns to counterparts in Austin.- Design and Develop AC characterization of digital interfaces on VERIGY platform.- Represent India Test team at design reviews, core team reviews and product support reviews.

In charge of handling reference program delivery for a niche memory design firm on LTX Fusion-HF platform

IntegraFlex HSD200/HSD100 checker program developer; VBA; IG-XL