IC Design and Verification Engineer having 9 year of industry experience, Specialized in Block/Subsystem/SOC level Verification.- Development of testbench environments using SystemVerilog & UVM.- Expertise in Verilog, System Verilog & UVM (Universal Verification methodology).  - Worked on various protocols like: AXI3, AXI4, AHB, APB, PCIe, Display Controller IP.- Development of uvm components like agents, checkers, monitors, scoreboards, coverage models etc.- Experience in SystemVerilog Assertions and Functional Coverage.- Full coverage analysis, that includes functional coverage, code coverage and assertion coverage.- Experience in GLS simulation and debug.- Extensive RTL debug using Synopsys VCS, Verdi, Cadence NCSim.