-->Working On different SoCs & Build Comprehensive Testbenches and develop tests to verify designs based on Test plan in SoC level, targeting 100% Coverage.-->Constrained-Random, Coverage-driven Automated Verification using UVM and Assertions with System Verilog.-->DV Test plan based on functional specification with estimated timelines for verification completion.-->Develop tests for Gate level simulation.-->Knowledge on Scripting to automated tool flows and report Generation.-->Strong knowledge of C/C++.-->Basic Knowledge on scripting languages : Python.-->RTL Coding, Verilog, System Verilog ,UVM and general design and debug.-->Frontend Digital design flows(ASIC/FPGA), Design & Verification tools(Xillinx-ISE, Vivado, Altera-Quartus, MentorGraphics- ModelSim, QuestaSim, Synopsys-Verdi, DVE & DVT), Synthesis, Timing closure, Simulation.-->Experience on Protocols: AMBA-AXI, APB, UART, SPI, I2C.