* Develop and implement thin film etch stop solutions for 10 nm and 7 nm nodes, improving device performance and reliability. * Create gapfill and hard mask solutions to enable patterning on 18A and advanced packaging applications, enhancing performance.* Support Front side IC patterning, resulting in a 15% reduction in defects and increased yield.* Conduct Failure Mode and Effects Analysis (FMEA) and Design of Experiments (DOE) to reduce defect density.* Strategically manage vendors to achieve cost improvements.* Interview, train, coach, and mentor new engineers in the dielectrics area, fostering a culture of growth and knowledge-sharing.

Fabricated and characterized nanomagnets at NIST Maryland's class 400 cleanroom using E-beam lithography and PVD. Pioneered a Surface Acoustic Wave (SAW) based nanomagnetic NAND gate device, leading to two publications on memory and logic device applications. Collaborated with NASA Langley Research Center for device characterization. Achieved high-quality Iron Gallium thin film growth, characterized using FMR, and determined dynamic magnetization parameters, resulting in a journal publication.