Established MultiCore processing pipeline for the Processor-In-Loop setup, which enabled 3 processor cores to access a shared memory region and perform their tasks effectively without any memory corruption.Utilized Single Instruction Multiple Data(SIMD) techniques in the Digital Signal Processor and efficient data transfer methods like DMA, for eliminating the Transfer time taken for moving data in between DDR and Cache, which significantly reduced the runtime of the application by 39%.Identified and rectified cache coherency issues that caused inaccurate program output, by implementing appropriate read and write invalidation techniques, ensuring data consistency across the system.

Worked as a Teaching Assistant for ML and AI courses, assisting students with their coursework and projects at IIT Tirupati. Gained deeper understanding of Machine Learning through active engagement with course materials and student interactions.