1.3 years of experience as a ASIC Physical Design Engineer.• Worked in 16nm, 28nm technology nodes.• Planning and Execution of Block level PNR (Netlist to GDSII)• Expertise in resolving various block level PNR issues.• Hands on experience in Innovus, ICC2.• Good knowledge in Static Timing Analysis.• Good knowledge on Low Power Design.• Good knowledge on digital logic and CMOS basics.• Good knowledge on Tcl scripting.• Basic knowledge in dbGet Commands.• Quick learner with Good analytical and problem-solving skills and able to work independently as well as part of a team.