Vincent Yu Email & Phone Number

Chicago, Il, Us

Miami, Florida, Us

Full stack FPGA developer for high frequency and ultra low latency trading systems.Optimized network stacks (Ethernet transceiver, MAC, IP, TCP, UDP) to achieve ultra low latency.Delivered computational intensive, high throughput, mid-latency FPGA systems.

Irvine, Ca, Us

200G Coherent Fiber Transceiver ASIC design. Optimzed digital signal processing intensive logic for speed/power/area.

Redwood City, California, Us

• Hands-on technical manager leading ASIC and FPGA development in the area of DSL noise cancellation.• Successfully delivered design prototype (Xilinx Virtex6 based FPGA flatform) and first pass working ASIC, ready for production and deployment at major telecom service providers.• Developed overall ASIC design plan, managed resources and tracked project schedules.• Effectively worked with system and algorithm teams to architect ASIC and major DSP cores.• Led digital design with custom DSP logic, AXI based switching fabric, DMA engines, multiple CPUs and peripherals.• Collaborated with firmware team on HW/SW partition and FFT and Correlator accelerator design.• Major contributor in technology, IP and tool vendor selection and negotiation.• Integration and lab bring up with ADC, LVDS, I2C, SPI, SD/MMC, Ethernet MAC, DMA and DDR PHY. • Drove physical design execution and product qualification with external design service partner.• Hands on experience with post silicon validation, silicon characterization and production qualification.

Palo Alto, California, Us

- Part of ASIC architecture team for generations of frame rate conversion SoC and IP cores used in millions of Digital TVs.- Designed and optimized on chip buffer subsystem to be area, bandwidth and power efficient.- Mapped complex algorithm to ASIC implementation in the area of motion estimation, motion compensation and 2-D sub-pixel interpolation.- Generated detailed module specification and mentored ASIC designers in RTL implementation and verification.- Implemented SoC internal bus structure and high speed LVDS interfaces.

Santa Clara, California, Us

- Joined AMD as part of ATI acquisition in 2006- Estabilished DTV's first ASIC team at Shanghai design center.- Recruited and mentored a team of design and verification engineers on ASIC methodology.- Led architecture and implementation of video compression IP.- Led ASIC implementation of ATI's first mobile TV SoC (DVB-H).- Major contributor to Nxtwave's VSB/QAM demodulator ASICs.- Designed and verified various FIR/IIR filter, timing recovery, DFE equalizer blocks.

Bsee, Electrical Engineering, Telecommunication

Msee, Electrical Engineering