Vineeth Kumar Email & Phone Number

3 years of experience in ASIC Physical Design field.Hands-on experience in complete backend flow - Logical Synthesis, Physical Synthesis, Floor Planning, Power Planning, Place & Route, Clock Tree Synthesis, SI Analysis, Signoff Timing Analysis and Timing Closure, Physical Verification and PERC, IR drop analysis and LEC.Strong fundamentals in Physical Design, ASIC flow, STA, EMIR and PV.Worked on TSMC 180nm , 90nm ,28nm , 22nm technology nodes from RTL to GDS-ll tape-out.Excellent hands-on over Cadence EDA tools.Good understanding in basics of digital design, cmos design and semiconductor devices

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  Vardhaman College Of Engineering (Vceh)

  Electrical And Electronics Engineering