SOC Design Engineer with 5 years of experience with main focus on static timing analysis and physical design. Skilled in working on industry-standard tools and methodologies to ensure the performance and reliability of complex graphics design from 14nm to 5nm nodes. I have hands-on experience with various STA tools, such as PrimeTime, Fusion compiler and ICC2, and proficiency in scripting languages like Tcl and Perl, allowing me to automate analysis flows and improve efficiency. In addition to my technical expertise, I am adept at creating and maintaining robust timing constraints, enabling seamless integration with the physical design process.