Vinodraj M B Email and Phone Number

1 year of experience as analog layout engineer at karmic design pvt Ltd. Undergone VLSI training in karmic design pvt ltd about standard cells such as inverter, NAND, NOR, XOR, MUX in 180nm, Analog layout in 45nm, layout dependent effects, Latch up, Matching techniques, Antenna effect, Electromigration, IR drop & Fabrication process. Presented a technical seminar on the topic of Metallization & CMP. Experience in building blocks like Amplifier, LDO, Charge pump, High speed clock, Clock doubler etc... Worked in different technologies such as TSMC 3nm, 4nm, t28, 45nm & f65. Expertise in debugging issues in physical verification like LVS, DRC, ERC. Physical verification tool used such as assura, PVS & calibre. Skills on EM - IR analysis, critical signals routing & shielding. Able to adapt to new technologies, provide extended support during critical times, Good communication & team player.