Virendra Singh Chauhan Email and Phone Number

1. Led SoC integration efforts, focusing on RTL coding and quality checks for SSD controllers (14nm and 5nm tech nodes).2. Owned Logical Equivalence Check (LEC), lint checks, and synthesis constraints for optimal timing analysis.3. Managed functional ECO implementations from RTL to post-layout netlist, ensuring backend delivery of sign-off quality.4. Streamlined workflows by automating design processes, enhancing team efficiency across multiple projects.Played a critical role in successful tape-out of chips, coordinating with backend, verification, and IP teams.

1. Completed on-site integration of third-party IPs at Samsung Korea for SSD controllers (4nm tech node), collaborating with global teams.2. Spearheaded power optimization initiatives using PowerArtist, resulting in significant power reductions for a key IP.3. Forecasted power consumption using PTPX at the post-layout stage, optimizing future project power requirements.4. Implemented LPDDR5 features in RTL Verilog with a focus on functional and lint checks.5. Verified unit-level functionality through detailed testing and code coverage analysis.Tools Used: Design Compiler, Formality, Conformal ECO, PowerArtist (PA), Primetime, SimVision, Verdi, PTPX (PrimePower), Spyglass Lint, Xcelium, Meridian CDC, RTL CompilerLanguages: Verilog HDL, C, C++, Python, TCL scripting, Linux Command Line, Make flow

1. Developed C-based validation test cases for firmware, ensuring comprehensive and robust post-silicon validation of eMMC chips.2. Demonstrated strong understanding of Jira workflows and effectively collaborated across cross-functional teams to streamline project processes.