Viswanathan J Email and Phone Number
1. Leadership and execution encompassing 18+ years in telecommunications, focusing on technical standards, requirement specification, software design, and development, along with comprehensive testing.2. Led deputations to prominent companies like Alcatel-Lucent in Sydney, Australia and New Zealand, Alcatel-Lucent Research Centre in India and Nokia-Bell Labs USA, Qualcomm Inc. in San Diego, USA, and NEC Corporation in Japan for requirement/system study, implementation, and performance analysis over a 4-year period. and collaboration with chipset vendors Freescale, Texas Instrument, Intel, and Qualcomm3. Extensive industry experience in designing and developing telecom software, implementing general design methodologies, and enhancing end products, including performance analysis and SDLC involvement in requirement analysis.4. Domain expertise spans across Signal processing and communication, 5G-PHY, LTE/LTE-A-PHY, LTE-EPC, WiMAX-PHY and end-to-end systems, WCDMA, wireless communication, wireless computing, wireless networking, and wired networking-L2 Ethernet switching.5. Recipient of client appreciation awards for exceptional service delivery.6. A collaborative team player with strong communication, analytical, relationship management, and coordination skills, adept at interacting across hierarchical levels within organizations and client locations to ensure smooth project execution.Skill Sets:Programming Languages:C, C++, Micro C, System Verilog, SystemCDevelopment Tools: Development Tools Modelsim, MATLAB, Jakarta-Ant, eXist (XML database), X-CAL driveTest Tool, Alcatel NMS tool, Alcatel-EMS, CM, Wire Shark Protocol Analyzer, TI CCS 5.3.1 Studio, Octeon NP SDK 1.8.1, QXDM, QACTWireless Standards: WCDMA, WiMAX, LTE/LTE-A, 5G-NR, SC-OFDMA, OFDMA, CDMA-EVDOProtocols/Datacom: LACP, STP, RSTP, MSTP, LACP, GVRPAssembly Language programming: Assembly language of TMS320c50, 8051 Microcontroller Operating Systems Platform: GNU/Linux Read Hat, RTOS-MvLinux, Embedded OS, TI OSEck, Smart DSP OSSystems on Chip Platform: TMS320c50, IXP 2400/2800, 2350 Network Processor, 8051 Microcontroller, Octeon Plus CN5860, DSP TMS320TCI6486, FPGA PCM MUX, CCPU PP50 XLR-732 board, TI SoCTurboNyquist DSP TCI6616, SoC ARM926EJ-S(QDSP), MCP Freescale 8157/56, TI SOC Kepler2 c66XX, Qualcomm Ten Silica DSP, FSMXXX, SDM85xx-SnapdragonScripting Languages: Perl, PythonStorage Technology: RDBMS-Oracle 8
Src Research Scholars Program
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Src Research Scholars ProgramMinneapolis, Mn, Us
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Founder And CeoHiflex Semiconductor Nov 2023 - PresentIn the era of next-generation networks, product research and development is entering an exciting phase, focusing on AI-driven advanced self-organized systems that leverage the capabilities of 6G wireless communication. The integration of Artificial Intelligence (AI) into the core of communication systems opens up new possibilities for self-optimization, real-time decision-making, and enhanced network orchestration. As we move toward the prototyping phase, this research places significant emphasis on the Physical Layer (PHY) of 6G communication, where cutting-edge technologies will enable ultra-high data rates, low-latency, and unprecedented reliability. At the PHY layer, 6G is expected to operate in the THz spectrum (100 GHz to 3 THz), offering massive bandwidths that were previously untapped. This will enable data rates in the range of terabits per second (Tbps), supporting future applications such as holographic communications, real-time virtual/augmented reality, and tactile Internet. Massive Multiple Input Multiple Output (MIMO), with thousands of antenna elements, will provide enhanced spectral efficiency, while beamforming will ensure ultra-precise signal directionality, even at higher frequencies. In this prototyping phase, key research areas include the development of AI-empowered signal processing algorithms at the PHY layer, which can dynamically optimize modulation schemes, resource allocation, and power control to ensure efficient utilization of the THz spectrum. Additionally, Reconfigurable Intelligent Surfaces (RIS) are being explored as a means to control electromagnetic waves, enabling smart propagation environments that enhance coverage and reduce energy consumption. The AI-based self-organized system, empowered by the 6G PHY layer, will revolutionize the future of wireless communication, delivering unprecedented levels of connectivity, intelligence, and adaptability.
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Senior Staff Engineer (Technical Manager/Technical Lead/Feature Lead)Qualcomm Oct 2022 - Oct 2023San Diego, Ca, UsLeadership and Execution, -Leads others, coordinates, and partners with closely connected teams to develop highly complex blocks, features, architecture, plans, schedules, and tests for vaguely defined tasks to ensure desired quality and design completeness, functionality, power, performance, and timing standards; recommends and drives improvements.-Applies deep and broad specialty knowledge to anticipate and identify complex architecture and design problems and helps others to resolve them; provides feedback during design reviews and collaborates with other teams to align plans and designs.-Displays deep knowledge in multiple areas; acquires advanced knowledge of industry trends, competitors' products, and advances in various engineering fields related to DSP products and technology (e.g., machine learning, modem); shares knowledge of multiple areas within their team and across teams working on similar products.-Stays abreast of current and future trends to make suggestions in strategic discussions within and/or across domains about the product/technology roadmap.-Communicates effectively with peers, senior leadership, and subordinates using written, verbally, and online communication; effectively tracks and documents issues, features, and design changes; reviews and writes clear and detailed technical documentation and feature descriptions for highly complex designs or difficult projects to guide users; reviews and provides feedback on more junior engineers' documentation.-Collaborated with key stakeholders and program sponsors to develop goals, set the prioritization of deliverables, and discuss necessary priorities and stakeholder needs.-Manage and takes responsibility for multiple small programs/technology with moderate complexity or a single complex program/technology by applying up-to-date program management knowledge to meet deadlines. -
Staff Engineer(Technical Lead/Feature Lead)Qualcomm Apr 2015 - Nov 2022San Diego, Ca, UsQUALCOMM FSM (eNB/gNB)-Hyper Dense Small Cell FSM: In this engagement, our leadership execution and technical architecture role played a crucial part in the implementation of new features within the LTE UL PHY cloud RAN architecture. Our team focused on integrating the ULCoMP feature into LTE small cells, preparing for commercial product release. This involved enhancing PUSCH receiver algorithms and inter-cell coordination in hyper-dense small cell environments, including DLCoMP implementation in LTE DL with Time Domain muting and eICIC. Through rigorous testing with multi-vendor UEs in lab and field settings, we demonstrated significant improvements in cell-edge UE throughput, aligning with 3GPP specifications.Our leadership ensured the inclusion of 5G-NR DL and UL Beam Sweeping with Hybrid Beam Forming, emphasizing synchronization elements like PSS/ESS/SS/BRS/BRS for gNB implementation. Additionally, our technical architecture role extended to the RF side, focusing on inner loop power control compliant with 3GPP standards. Thorough testing using Agilent Network Call Box validated the effectiveness of the adaptive power control method in both lab and field environments, showcasing our commitment to delivering robust and standards-compliant solutions.MSM SDM8550-ADSP: In this project, as a leader and manager, I led the customization of telephony and LTE/LTE-A, 5G/NR, and Bluetooth (LEA) interfaces, overseeing the optimization of audio graphs, enhancement of noise suppression algorithms, and analysis of signal processing system performance. Additionally, I directed the development of an Android application to facilitate LEA/BT/Telephony (LTE/LTE-A, 5G) APIs for signaling and control plane operations, including the implementation of ANC feature for the audio DSP system. This involved both static and adaptive ANC for various ambient noises, with software development for performance analysis across different channel conditions..
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Technical LeadTata Consultancy Services Nov 2011 - Apr 2015Mumbai, Maharashtra, InNokia, Texas Instruments, Freescale Semiconductor, Qualcomm: The project scope involves the comprehensive development and deployment of advanced functionalities for the PUSCH receiver, guided by effective leadership execution. This includes algorithm development for critical receiver functions like channel estimation, demodulation, and decoding. Leadership ensures meticulous design of the receiver architecture, optimizing signal processing pipelines, synchronization mechanisms, and error correction techniques. Performance optimization, interference mitigation, and compatibility testing are prioritized under leadership to enhance signal quality, reliability, and interoperability. Integration with baseband processing is overseen to seamlessly integrate the receiver module with other functions. Field testing and validation are conducted to validate performance in real-world environments. Documentation and reporting are diligently managed to comply with internal and regulatory standards. Effective collaboration and communication with cross-functional teams ensure synergy and innovation throughout the implementation process, fostering successful project outcomes. Additionally, leadership directs the implementation of radio-based FDD/TDD PHY synchronization and the realization of cloud LTE-RAN in small cell hyper-dense networks, along with various enhancements and optimizations to the PUSCH receiver algorithm and functionality.Technical Roles and Responsibilities with Design & Development for commercial release for Freescale Semiconductor, Qualcomm, Nokia’s Network with Texas Instrument products developments -
Module Lead/Project LeadNec Technologies Aug 2009 - Oct 2011Tokyo, JpThis project involves the comprehensive creation of requirement specifications, architectural design, system design, high-level design, and fresh development of the L1 Controller for LTE physical layer, with a focus on FAPI compliance for NEC LTE products. Under effective leadership execution, the L1C mode is meticulously designed to incorporate semi-static information from the PHY layer, with uplink calculation serving as the master. The L1 controller undergoes rigorous implementation and testing for both uplink and downlink channels, particularly tailored for femto eNB solutions. It is ensured that the L1 controller remains interoperable with any third-party LTE MAC and PHY solutions. Moreover, leadership directs the implementation of the L1 Controller in three distinct modes: L2 master, L1 Master, and semi-static information held in L2, with PHY uplink calculation held in L1. This approach ensures robust functionality and adaptability to diverse network configurations, thereby contributing to the success of the project.This project involves leadership execution and a pivotal technical architecture role in creating requirement specifications, architectural design, system design, high-level design, and the development of Traffic Offloading. Specifically, our focus is on implementing Iu-PS SIPTO, which acts as the Traffic Upload function at the Iu-PS interface of the 4G network, adhering to 3GPP standards. Our leadership ensures that this product effectively frees core network elements from data traffic, offloading it locally on eNBs. This strategic approach enables the development of the data plane independently from the control plane, thereby reducing core network development costs. Additionally, our technical architecture role involves designing and implementing EPC nodes like MME, eNodeB, P-GW, and S-GW. These nodes serve as stability check environments and integration nodes for the LTE-EPC system. -
Senior Software EngineerCapgemini Engineering Oct 2006 - May 2009Paris, Île-De-France, FrIn this project, leadership execution and a crucial technical architecture role were integral. The scope encompassed the design and implementation of firmware interfaces for the TMS320ITC6486 processor and Octeon Plus CN5860. Our leadership ensured efficient coordination and management of the project, while our technical architecture role involved crafting robust firmware interfaces that met the stringent requirements of both processors. Furthermore, porting the boot loader for DSP TMS320ITC6486 and Octeon Plus CN5860 was a critical aspect of our responsibilities. We meticulously considered design considerations for a multi-core processor on Octeon Plus CN5860 and DSP TMS320ITC6486, ensuring seamless integration and optimal performance. Through effective leadership execution and technical architecture expertise, we successfully delivered a comprehensive solution that met project objectives and exceeded expectations. In this project, our leadership execution and technical architecture role played crucial parts in enhancing mobility features and optimizing the existing code base. Our leadership ensured effective coordination and management, guiding the team through the implementation of new features and bug fixes. We actively contributed to bug fixing at various layers, including PHY, MAC, and control paths, and addressed issues with the ASN gateway at layer 3. Additionally, our technical architecture role involved designing and implementing MAC layer mobility mechanisms such as fast base station handover and micro-diversity handover, ensuring seamless integration with the existing system. We also led the porting tasks, including the integration of the IP header compression algorithm and IXP NP data accelerators (ROHC protocols), optimizing system performance. Through our leadership execution and technical expertise, we successfully verified the WiMAX (MAX-CS) performance across different types of service, ensuring the project's success. -
Design And Development EngineerTata Elxsi Oct 2005 - Nov 2006Bangalore, Karnataka, InIn this project, our leadership execution and technical architecture role were pivotal in driving the development of the PHY stack for the base station. We led the design and implementation of a comprehensive set of modules adhering to the 802.16e standard, utilizing the C programming language. Additionally, we leveraged MATLAB for simulation purposes, ensuring functional verification of the embedded development. Our technical architecture role involved designing the system with flexibility in mind, enabling seamless portability of the embedded code to various hardware platforms as a library. Through effective leadership and technical expertise, we ensured the successful implementation of the project's objectives, meeting the stringent standards of the 802.16e specification while maintaining adaptability for future hardware integration.
Viswanathan J Education Details
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University Of Minnesota College Of Science And EngineeringElectrical And Computer Engineering(Vlsi Design With Ai) -
College Of Engineering, GuindyInformation Technology(Networking And Communication)
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Madurai Kamaraj UniversityElectronics And Communications Engineering
Frequently Asked Questions about Viswanathan J
What company does Viswanathan J work for?
Viswanathan J works for Src Research Scholars Program
What is Viswanathan J's role at the current company?
Viswanathan J's current role is Founder & CEO | Wireless PHY| Digital Signal Processing |Firmware| PHY BaseBand Design|Product Architect | Product Development |System Engineering |Communication Systems | SoC Design |RF Design |Parallel Computing.
What schools did Viswanathan J attend?
Viswanathan J attended University Of Minnesota College Of Science And Engineering, College Of Engineering, Guindy, Madurai Kamaraj University.
Who are Viswanathan J's colleagues?
Viswanathan J's colleagues are Kathryn Zhang, Nehil Shreyash, Ralph Cavin, Coco Lin, Scott Dobson, Latanya Holmes, Kristina Ellison.
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