• Experienced Verification and Functional Safety Engineer with a robust background in the IP industry.• I have honed my skills in ensuring that IP designs function correctly and that products operate safely and reliably throughout their lifecycle.• Good experience in Design Verification flows: defining test plans and writing constrained random test cases to find RTL bugs.• Excellent experience in creating automation scripts for regression using Perl to enhance DV efficiency.• Strong experience in cross-functional collaboration with cross-functional teams which include the Design team, Architecture, Safety team, and Tool vendors.Skill Set : Verilog, System Verilog, Linux, FPGA, VLSI concepts of low power, C, C++, Python, Synthesis of design on FPGA, VCS Simulator, GVIM, UVM.
Listed skills include Computer Networking, Java, Microsoft Word, Sql, and 12 others.