Vivek Packiaraj Email & Phone Number

Chennai, Tn, In

Chandler, Az, Us

Managing a team of ASIC designers, with broad based skills spread out into Digital IP design, Verification, Synthesis, STA, ATPG, APR/PNR and DRC, LVS, Full chip Layout. Be responsible for MCU8 New product development in close collaboration with concept/DOS, RTL full chip Integration, IP Design, Full chip/IP verification, mixed signal verifications, Synthesis, STA, ATPG, APR, Analog IP delivery's and taking it to GDSII (after DRC, LVS)Hands on On Project leading, RTL integration, Verification closure overseeing, signed off Synthesis, STA and ATPG on several rev A to RTP chips. Chip Lead activities for many chips now Released to Production. (RTP)End to End support from design of AVR8 chips, all aspects of chip design, streamout, and aftermath support for test, validation support closure until released to productionHands-on on design, Synthesis, STA, ATPG and basic PNR flow. Worked as a Synt, STA, DFT, UPF signoff for 6 years for MCU32 and MCU8. Managing Design, Verification, Implementation including all aspects of chip design, reviews enabling high quality and timed streamout. Preparing the database for audit standards and qualification. People Management, Quarterly 1:1, goal settings, alignments with Business objectives and QSRs. Cross site collaborations, alignment preparations and executions.

Chandler, Az, Us

+ Chip lead activities+ Leading the spec, integration, implementation up to stream-out. + Leading Integration efforts include full chip integration, rtl, gls regressions, IP bug fixes/releases. + Leading Implementation include synthesis, STA, Equivalence, ATPG insertion, ATPG corner sims+ Production support on scan pattern fault analysis with tetramax.+ Complete full chip STA responsible for AVR- 8 bit based new tiny micro-controllers.+ Timing ECO's+ Full-chip level constraint development and check.+ Complete set of constraints includes clocks, input and output delays, clock latency, clock ...uncertainty, set-case-analysis, clock and input transition, output load, max and min delay, false ...path exceptions and multi-cycle exceptions paths etc,.+ Synthesis, scan insertion and expected deliverable to PD team.+ Responsible for reviews from implementation to STA including libraries.+ ATPG pattern generations, simulations and debug.+ Equivalence+ Library checkouts, version ownership.+ Top level Specification coverage, RTL chip level integration work.+ Overseeing RTL regressions, GLS support.

San Jose, Ca, Us

Micro-Controller design including digital interface, controller, digital logic design and verification for flash memories, design/verification for in-build Micro-controllers for various devices, ISA, Micro-architecture design (control,data & address path), RTL, functionality coverage, BIST and basic synthesis.+ Have participated in Digital Front End and Mid End (synt/STA) for 10 + tape-outs at Full Chip+ IP Design, improvements, tradeoffs, architecture improvements and feasibility projects+ ISA design (Instruction Set Architecture)+ STA (standalone and DMSA) & SI Delay, SI Noise+ Synthesis (Topo and Non Topo)+ Constraints Bring up (Full chip execptions, MCP, False paths, IO constraints)+ ECO (complex Timing and functional) , fixing setup/hold and drc violations, revision tapeouts+ UPF (power domain definitions, PST, Levelshifter and ISO policies)+ LEC using formality/Conformal ASIC+ Hands on in power estimation and analysis using PTPX.+ Full chip integration with Analog + Chip level functional Verification setup with modeled Analog behavior + BIST, power up design in full chip+ Gate Sim for Timing closure using Dynamic Simulations+ Coverage analysis+ Module level verification in Verilog.+ Prepared the Verification plan and coded the verification testbench and testcase.+ Co-simulations to verify the communication between analog and digital module.+ SPI, I2C protocols

Santa Clara, California, Us

Configurable Processor building blocks design for Hardware accelarators used in DTV's, VLIW basics architecture and functional units (FU) , configurable bus protocols enhancements and functional verification+ Configurable Bus Enhancements+ VLIW Architectures+ CIO/OCP Bus Protocols+ Functional Unit designs for Vector Processors

Linköping, Östergötland, Se

Dept: ISYApplication Specific Instruction Set Processor Design:- Study, Design and Implementation of ASIP, used for DSP tasksThis concept features hardware structured approach for implementation of processor core from minimal instruction set, encoding standards, hardware mapping, and micro architecture design,coding conventions, RTL,verification and burning into a FPGA. The goal is to design an ASIP processor core (Micro architecture design and RTL) which can perform DSP task, e.g., FIR.+ ASIP Design for DSP tasks+ ISA Design+ Micro-Architecture Design+ RTL+ VHDL+ FPGA hardware mapping

Masters In Electrical Engineering, Embedded Electronics And Computers

Be, Electrical And Electronics Engineering

Xii, Higher Secondary

X, Icse