Vivek Packiaraj Email & Phone Number

A highly motivated and quality-oriented Technical Manager with over 19 years of experience in various aspects of chip design, including RTL design, synthesis, STA, microarchitecture design, basic verification, full chip integration, equivalence, ECOs (timing and functional), and PNR. My project experience spans a wide range, including Serial Flash and 8-bit and 32-bit microcontrollers. I have successfully delivered over 30 products, from specification to GDSII, and have supported product teams in bringing designs to market readiness.A role model People Manager and technical expert, adept at leading teams from new college graduates to experienced managers, with hands-on experience across multiple domains.Overseeing hiring processes, developing training strategies, defining job responsibilities, budgeting, conducting quarterly salary reviews, and holding team one-on-one meetings.Creating and aligning development plans with Management business goals (MBO), collecting status updates, organizing team meetings, and recognizing team achievements.Led the development of multiple chip projects, including new family introductions and major/minor revisions, managing a team of 15-20 members across global centers.Managed the complete ASIC digital design cycle, encompassing specification, Instruction Set Architecture (ISA), micro-architecture bring-up, RTL design, verification, synthesis (using Synopsys Design Compiler), Static Timing Analysis (STA) with Synopsys PrimeTime, gate-level simulation, functional and timing Engineering Change Orders (ECOs), equivalence checking (using Formality/Conformal), clock tree specification, and PTPX flow.Extensive experience in the digital design cycle, including front-end design and verification, synthesis, and STA sign-off for various tape-outs on micro-controllers and flash memory chips successfully released to the market.Proficient in designing and verifying 8-bit and 32-bit general-purpose micro-controllers (AVR/ARM) and serial/data flash chips.Hands-on experience with Static Timing Analysis (PrimeTime) and Synthesis (Design Compiler) across multiple projects, including full-chip level constraints, clock definitions, clock path/data path buffering analysis, scan insertion, and timing ECOs.Specialized in multimode multi-scenario (DMSA) timing analysis.Expertise in the full development cycle of Application Specific Instruction Set Processors (ASIP) tailored for specific application profiles.

Listed skills include Verilog, Asic, Microcontrollers, Vhdl, and 18 others.