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Vedant Talnikar Email & Phone Number

Lead Design Engineer at Cadence Design Systems
Location: Pune, Maharashtra, India 5 work roles 3 schools
1 work email found @cadence.com LinkedIn matched
✓ Verified August 2026 4 data sources Profile completeness 86%

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Current company
Role
Lead Design Engineer
Location
Pune, Maharashtra, India
Company size

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Quick answer

Vedant Talnikar is listed as Lead Design Engineer at Cadence Design Systems, a with 10387 employees, based in Pune, Maharashtra, India. AeroLeads shows a work email signal at cadence.com and a matched LinkedIn profile for Vedant Talnikar.

Vedant Talnikar previously worked as Design Engineer II at Cadence Design Systems and Design Engineer at Cadence Design Systems. Vedant Talnikar holds Master Of Technology - Mtech, Embedded Systems from Bits Pilani Work Integrated Learning Programmes.

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{first_initial}{last}@cadence.com
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Profile bio

About Vedant Talnikar

Working in DSP (Algorithms & processors) domain as a Lead Design engineer for around 6+ years. I have a mix of experience in implementing Neural Network inference models on DSPs, Optimization of various audio decoders, post-processing components from Dolby on DSPs, and tuning the system for better performance. Most recently worked on implementing and optimization of NLP NN architecture MobileBert on Tensilica DSP. Highlights:1) Good hands-on experience in optimization, benchmarking, and system performance tuning of various algorithms on DSP processors.2) Good understanding of Porting NN modules on DSP processorsSkilled in C, Perl, Bash scripting, DSP algorithms, Embedded Systems, and Artificial Neural Networks. Strong engineering professional with a Master of Technology (MTech) focused in Embedded Systems from BITS Pilani.

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Cadence Design Systems
Cadence Design Systems
Lead Design Engineer
Pune, MH, IN
Website
Employees
10387
AeroLeads page
5 roles

Vedant Talnikar work experience

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Lead Design Engineer

Current

Pune, Maharashtra, India

In this new role will be responsible for Leading project execution i.e. taking full ownership of optimizations, estimations, Implementation, and project tracking.Lead a team responsible for the Dolby Atmos for Cars project from estimation, planning, development, testing, and release cycle

Jul 2022 - Present

Design Engineer Ii

Pune, Maharashtra, India

1) Responsible for HEAAC decoder component in Dolby MS12 Multi-steam Decoder framework - for performance, memory and code size optimizations on Tensilica HiFi3 DSPs. - for integration, API development, testing and bug fixing.2) Implementation of Natural Language processing(NLP) Neural network architectures on HiFi5 DSP - worked on benchmarking and enabling of inference phase of transformer NN architecture based NLP applications like MobileBERT (used in Q&A chat bots) & transformer for language translation - Implemented end to end inference phase of transformer encoder-decoder architecture for language translation in C. Optimized it on Tensilica HiFi5 DSP for performance and memory.3) Further, worked on fixing issues in gcc to clang compiler transition for several Audio codecs.4) Developed perl scripts for improving and auto-generation of ISA html documentation of DSPs.

Sep 2020 - Jul 2022

Design Engineer

Pune Area, India

- Responsible for performance optimization and benchmarking of Dolby MAT encoder and Dolby DAP component in Dolby MS12 Multi-Stream Decoder (Dolby Atmos) audio framework on Tensilica HiFi3 DSP- Worked on API development, performance optimization, testing and integration of Fader component in Dolby Harmonious (Home Audio)- Actively involved in optimization of NN Activation functions tanh & sigmoid on Tensilica HiFi3 DSP. - Worked on development of perl script based frame work which creates html documentation of Instruction set Architecture (ISA) of HiFi5 DSP. This is now widely used across teams for DSPs like HiFi4, HiFi1, Fusion etc.

Jun 2018 - Sep 2020

Intern

Pune Area, India

Study and Estimation of inference phase of Neural network in ASR domain like Wavenet, DeepSpeech on Tensilica DSP processors.C implementations and optimization of neural network layers like fully connected, GRU, LSTM, for accurate performance estimations.

Jun 2017 - Dec 2017
Team & coworkers

Colleagues at Cadence Design Systems

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3 education records

Vedant Talnikar education

Bachelor Of Technology (Btech), Electronics And Telecommunication, 9.51 Cgpa With Distinction

Activities and Societies:  Multimedia Secretary - Student Council VIT Pune 2016-17.  Executive Committee member - ‘VIT Mirage Campus.

Education record

Gujrati Highschool , Nanded
FAQ

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What company does Vedant Talnikar work for?

Vedant Talnikar works for Cadence Design Systems.

What is Vedant Talnikar's role at Cadence Design Systems?

Vedant Talnikar is listed as Lead Design Engineer at Cadence Design Systems.

What is Vedant Talnikar's email address?

AeroLeads has found 1 work email signal at @cadence.com for Vedant Talnikar at Cadence Design Systems.

Where is Vedant Talnikar based?

Vedant Talnikar is based in Pune, Maharashtra, India while working with Cadence Design Systems.

What companies has Vedant Talnikar worked for?

Vedant Talnikar has worked for Cadence Design Systems.

Who are Vedant Talnikar's colleagues at Cadence Design Systems?

Vedant Talnikar's colleagues at Cadence Design Systems include Benoit Mallol, Sharath Y P, Flowers Gus, Abhilash Mohanty, and Mayank Chaturvedi.

How can I contact Vedant Talnikar?

You can use AeroLeads to view verified contact signals for Vedant Talnikar at Cadence Design Systems, including work email, phone, and LinkedIn data when available.

What schools did Vedant Talnikar attend?

Vedant Talnikar holds Master Of Technology - Mtech, Embedded Systems from Bits Pilani Work Integrated Learning Programmes.

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