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• Ten years hands-on experience and a solid understanding in all stages of latest industry physical design flows and methodologies• Strong fundamentals in digital logic design with expose to design using HDL languages Verilog/System Verilog, functional simulation, and logic synthesis• Expertise with RTL coding netlist design and verification, partitioning, place and route, ATPG, DFT insertion, formal equivalence checking, CLP, STA timing closure, EM/IR power analysis, physical design verification flows and post silicon validation• Strong background and experience in block and full-chip implementation and verification with industry EDA flows and tools• Strong understanding in RTL2GDS flows and design tape out test chips in 22nm, 28nm, 55nm and 65nm technologies and ASIC chip in 14nm. Trained/educated on 5nm process.• Solid understanding of clock domain crossing, synchronous/asynchronous design and timing, multi power/voltage domains, low power design, high speed timing closure, UPF/IEEE1801 power intent• Fundamental knowledge of System Verilog and verification methodology• Proficiency in programming and scripting languages Python/Perl/Tcl/Make
Nordic Semiconductor
View- Website:
- nordicsemi.com
- Employees:
- 1317
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Nordic Semiconductor
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Staff R&DNordic Semiconductor Jul 2023 - PresentTrondheim, No
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Sr. Physical Design EngineerEncore Semi, Inc. Dec 2021 - Jun 2023San Diego, Ca, UsMarvell Technology customer• Drive RLMs/Blocks through all stages of physical design, from postFEP netlist to floorplan, partitioning, CLP, power grid generation, place and route, CCopt to SOM/TSO timing sign-off• Generate ETM timing for child blocks and run hierarchy parent block implementation• Complete UPF power content file for RLMs blocks and run quality check using CLP conformal• Work with the design team for FX14 Dflow methodologies bring up and validation, resolve design and flow issues relating to physical design, identify potential solutions and drive execution• Assist to integrate the top chip, C4 bump assignment, RDL/PST routing using ImageToolBox, run full routing to check for congestion, routable or any potential routing issues and report to top chip team• Pull in Blocks/RLMs from other PD team to take a postFEP netlist through all stages in the flow/recipes• Derive workable timing solution for high-speed ARM CORTEX/A35cpu, work with timing team on timing constraint adjustment to archive timing clean in hierarchy/flat run.• Collaborate with PSI team and run PSI flow for blocks to analyze/debug EM/IR, hot-spots, high compression, in-rush, power up issues to drive solutions -
Design EngineerMobile Semiconductor Feb 2012 - Dec 2021Seattle, Wa, UsRTL frontend chip design and verification• Planed and reviewed test chip verification to ensure covering all test cases and memory features.• Developed and maintained BIST(Built-in-self-test) compiler to support on-chip SRAM with varying size and ensure full test coverage.• Built scalable and synthesizable RTL top and block level test chip netlist to validate the embedded memories.• Managed logic synthesis, DFT insertion, design verification and resolving all bugs on RTL test chip netlist.Physical chip design and verification.• Performed block level/full chip level for floor-planning, power-grid creation, placement, CTS, routing, congestion analysis, and timing closure through sign-off.• Responsible for functional verification and gate-level simulation for final netlist.• Coordinated with mask designer to solve any DRC errors on IP/memory for DRC/LVS at full chip level.• Run the final gate-level netlist testbench simulation to verify chip functional correctness.• Performed final verification for full chip in preparation for GDS tape out (DRC, LVS, DFM, Density Fill, Antenna) delivery to foundry.Post-silicon validation• Established silicon verification flow, including stimulus vector setup, silicon debugs, failure analysis.• Developed Python/Perl automate scripts to run silicon tests, collect and post-process massive test data.• Reviewed and participated in silicon data and test reports weekly with the test engineer team.• Mentored and assisted test engineer teams for debugging and accelerating silicon test progress.
Vu Lam Skills
Vu Lam Education Details
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University Of WashingtonElectrical And Electronics Engineering -
University Of Washington - Engineering Co-Op ProgramElectrical Engineering
Frequently Asked Questions about Vu Lam
What company does Vu Lam work for?
Vu Lam works for Nordic Semiconductor
What is Vu Lam's role at the current company?
Vu Lam's current role is Physical Design and Verification Engineer.
What is Vu Lam's email address?
Vu Lam's email address is vlam2@uw.edu
What is Vu Lam's direct phone number?
Vu Lam's direct phone number is +140821*****
What schools did Vu Lam attend?
Vu Lam attended University Of Washington, University Of Washington - Engineering Co-Op Program.
What skills is Vu Lam known for?
Vu Lam has skills like C, Matlab, Testing, Vhdl, C++, Physical Design, Logic Synthesis, Rtl Design, Timing Closure, Verilog, Fpga Prototyping, Python.
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