Amit Vyas Email & Phone Number

San Jose, Ca, Us

United States

Leading a global team for Software, Silicon, and Boards applications

California, United States

Led FPGA hardware and software product management, soft and hard IP strategy, vendor management and early sales

Fremont, California, United States

Sunnyvale, California, United States

Co-founded AI Health, an idea curated during MBA school nights, that helps to detect and prevent embezzlement using analytics in healthcare offices. Cloud based, HIPAA compliant, SaaS solution deployed on AWS that empowers doctors to identify possible embezzlement by analyzing their day-to-day financial transactions. Led off-shore SW development team to bring the product to App Store and in healthcare offices.

San Francisco Bay Area

Led Intel PSG 14nm and 10nm AgileX FPGA products execution from architecture/design to post-silicon manufacturing, product binning, PPA optimization, process technology evaluation, silicon-package co-design and hardware/software IP modeling. Led outsourcing engagements and execution of multi-chip STA closure that included FPGA, Serdes, and HBM. Applicable skills:Hands-on technical leadershipStrategyCross-functional team leadershipTeam ManagementProgram ManagementProject ManagementChange ManagementRisk ManagementTalent ManagementCollaborative Problem SolvingStakeholder managementData AnalysisRetentionBusiness StrategyBusiness DevelopmentStrategic PlanningMarketing

United States

Successfully led cross-functional global team through the development lifecycle of timing modeling and post silicon correlation/binning for Stratix 10 product family.

United States

● Led definition and development of power & performance projections for tablet/mobile SOCs. Led cross-functional team and worked closely with strategic planning, marketing, senior corporate management and architecture teams. The SOC achieved successful PRQ for Intel and is used in Surface tablets & Alexa ● Managed a highly experienced team responsible for developing CAD algorithms & tools to improve design efficiency, TTM and BOM cost optimization for tablet/mobile SOCs

● Architected methodologies & flows for reliability sign-off for Intel’s entire line of SOCs and High Speed IOs in Digital Home space shipping well over a million units (IPTV, GoogleTV, CE3xxx, Puma6) tools like ICC, PTPX and PrimeTime for design analysis, QA and final sign-off before shipping to the fab.

● Developed Reliability verification flows and timing methodologies for Intel’s Digital TV/set-top box line of products. Responsible for analyzing & signing-off on EM, IR & ESD robustness for the place & route designs, custom IP blocks like PLL, DDR and GPIOs and Full chip SOC database.

● Owned QA flow development, production releases of all IP portfolio and design automation solutions for the company. Worked directly with Internal Engineering teams, foundry partners & EDA tool vendors

Master Of Business Administration - Mba

Core Courses: Marketing Analytics Decision Models Turnarounds, Mergers & Acquisitions Pricing Corporate Finance New Venture Finance Game.

Analog Ic Design, Analog Ic Design

Design of an advanced CMOS OPAMP, a compact low-voltage low-power OPAMP, and high-performance CMOS comparators

Master'S Degree, Computer Engineering