Intern
Current-Working as Design and Verification intern, myrole involves developing a UVM-based testbencharchitecture aimed at designing and verifying the RISC V RV32I processor using Assembly level programming( base ISA ), alongside verifying the modules by using UVM tb and developing multiple testcases and scripting using Perl.Hence aiming to design a perfect RISC-V Processor SoC using the tools Synopsys Design Compiler, QuestaSim, Verdi.