David Wager Email & Phone Number

Williston, Vermont

Design SRAM and other arrays as needed for customers.Staff, setup, and manage Mobile-Semiconductor's Vermont design center.

Essex Jct, Vt

Built design software infrastructureWorked on SRAM design and simulated for verification.The startup, SiVision, failed for financial reasons.

Williston, Vermont

Updated and maintained 10nm bit cell kits under contract to for IBM.

Essex Junction, Vermont

Designed and managed competitive arrays for ASIC offerings in 350nm to 14nm (Finfet) technologies. Technically managed 11 external designs (180nm to 45nm), set technical specs, and intergraded the results into ASIC offerings. • Developed and tuned the read and write features of a compilable ternary CAM in 14nm (FINFET) and 22nm technologies as technical lead of an offsite team, splitting up individual paths in the array and tuning many paths simultaneously, improving the TAT and access time to accomplish the customer’s target.• Led a technical team, including engineers in IBM China, to develop a dual-port compilable SRAM in 32nm technology, incorporating innovative tracking timing circuits that increased performance 15%. • Provided 8 compilable SRAM and ROM arrays in 45nm and 65nm technologies by leading technically a vendor (ARM) under contract. This required Communicating requirements, conducting design reviews, suggesting design updates, creating / developing IBM proprietary timing rules, doing all physical / electrical verification and integrating flows into IBM ASIC design system. • Debugged several 65mn and 45nm functionality / low yield issues with test-site and customer hardware, delivering a qualified competitive ASIC offering.• Drove development of externally designed ASIC compilable memory array timing and power rules flow, enabling external designs to be integrated into the in-house static timing tools. • Developed early SRAM cells test-site for 65nm technology prior to infrastructure being available while meeting a tight test site schedule.• Developed the methodology to allow external arrays integration by setting requirements, doing design reviews, making physical changes, suggesting updates, creating / developing IBM proprietary timing rules, doing physical / electrical verification, and integrating into IBM ASIC design system for qualification.

Burlington, Vermont Area

Compilable Memory Design Engineer

Essex Junction, Vermont

Characterized and debugged early NMOS and 1um CMOS circuits. Built all test structures for DC and high frequency testing including soldering surface mount components. Developed and built many test fixtures for characterization and maintained all equipment in the lab. Performed physical layout for logic blocks in early part of design cycles.

Bachelor Of Science (Bs), Electrical Engineering, 3.47

Activities and Societies: • Tau Beta Pi, National Engineering Honor Society

Associates, Electrical Technology, 3.65