Walter Nestor Petters Guse Email & Phone Number

Digital IC Design Engineer with 10+ years of experience in architecture and micro-architecture definition, RTL coding (SystemVerilog), testbench & SVA coding, simulation/debugging including back-annotated GLS, preliminary synthesis, timing & power analysis, python & bash scripting for automation and IP integration (8-bit CPU, PCIe) and background in functional verification (UVM).During this period, I worked closely with analog architects and designers to define control and data interfaces in the analog/digital boundary, with verification engineers to develop verification plans and debug issues and with managers in schedule development and resource allocation. Also worked in a multi-disciplinary team to define high-level specifications for a medical device prototype.For testing engineering samples, I defined and implemented a self-checking, automated test platform using PC + Python + FPGA + Lab equipment.In other tasks, I assisted in improving the company design flow and mentored newcomers on it.I´m execution-oriented and have a strong sense of ownership. Enjoy working in teams and discussing issues & finding solutions. Good interpersonal skills.

Listed skills include Linux, Verilog, Microcontrollers, Windows, and 16 others.

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  Universidade Regional De Blumenau

  Telecommunications Engineering