• Developed new ALD processes and CIPs for logic metal gate applications, and deployed at customer sites. • Developed strategy for project execution, designed and ran customer demos, and generated internal and external documentation.• Extensive use of JMP for experimental design and statistical analysis.• Interacted with customers to recommend product and process improvements and resolve difficult process engineering issues.• Established the lab’s electrical test capability for Si and high-mobility channel MOScaps.

• Coordinated the introduction of new products, product improvements, and product modifications. • Improved existing processes by reviewing objectives and specifications, evaluating proposed changes, and making recommendations. • Implemented BKMs & CIPs at customer sites, executing necessary actions and modifications.• Established client confidence and protected operations by maintaining confidentiality, presenting potential solutions through on-site visits, and developing strategies to deal with the unexpected. • Prepared material summarizing the roles and desired properties of films in an integration scheme. • Performed vendor process qualifications on new ALD systems and post chamber changes.• Recommended changes to the customer’s HVM and development processes to correct growth per cycle, uniformity, elemental composition, and contamination nonconformities in response to SPC events.• Resolved escalations and communicated CIPs remotely and through on-site intervention.

Assessed technology reliability to support development of new, extensions of, and modifications to CMOS, BiCMOS, and MEMS technologies. Worked closely with technology development, manufacturing engineering, circuit design, quality engineering, and in-line test. Carried out qualifications applying industry standard and IBM specific criteria. Applied, modified, and developed stress methodologies and lifetime models. • Designed device layout, stressed, and analyzed time dependent dielectric breakdown (TDDB) and process induced damage failure mechanisms to project semiconductor device lifetime within given operating conditions. • Wrote data analysis code for hot carrier injection, bias-temperature instability, TDDB, and Vbd stresses.• Provided consultation to manufacturing during process induced damage problem solving activities.

Reduced waste and encouraged workflow as a member of the photolithography track team. Lead problem solving teams of tool engineers, process engineers, level owners, engineering techs, and maintenance technicians following lean manufacturing process management. • Owned all tools in the DNS toolset including those that process color filter array pigmented photoresist. Provided defect reduction, cost savings, line support, process development, and equipment engineering. • Owned line support for fleet of photo tracks. Responded to yield loss events caused by tool failure or process incongruity, initiated structured problem solving to identify root cause, and implemented standard work if necessary to prevent reoccurrence. • Provided and coordinated direction to tool control and process issues that had been referred to engineering. Understood failures and proactively implemented and communicated action plans.

Conducted undergraduate and graduate level laboratories for the classes Microlithography Systems and Microlithography Materials and Processes. Prepared materials and equipment, presented pre-lab information to students, supervised and coordinated experiment direction, and graded student work. Drafted new laboratory procedures and pre-lab reading material.

Characterized photolithographic processes for liftoff resist film stacks with critical dimension swing curves and optimized for the lowest rate of change and largest undercut. Used spin speed curves to characterize existing spin-coat recipes and optimized for desired thickness and uniformity. Created templates for future spin-coat recipes citing resist and target thickness as variables. Characterized thickness and uniformity differences between spin coaters. Quantified thickness loss differences between spray and puddle develop recipes.

Designed, built, and tested experimental cochlear implant perimodiolar electrode arrays. Tested drug delivery electrode for possible malfunctions. Conducted a worst-case scenario experiment involving repeated insertions of electrode array and instrument misuse and ran telemetry measurements to test for possible causes of post-operative electrode failure.

Improved throughput by using statistical analysis to show that control wafers could be moved from a capacity-limited machine to a machine with available capacity. Worked to qualify a plasma etch chamber for production. Edited plasma etch process to increase sidewall angle control. Reduced the process time of a photoresist plasma strip.